This paper presents three new power-efficient designs of ternary SRAM using carbon-nanotube-field-effect-transistors (CNTFETs). Two the proposed are cycle-operator based and third design is buffer-based. The cycle operators buffer used in consume low power as they use two supplies for operation. Ternary logic implementation CNTFETs largely being lately due to advantages it provides terms reduce...

This article proposes a jitter-aware decoupling capacitors placement optimization method that uses the genetic algorithm (GA). A novel for defining target function in regard to power delivery network (PDN) and source-induced jitter (PSIJ) based on GA-based tool is proposed. The proposed can provide an optimum economic solution number of use PDN reach impedance. Then, by modifying with our metho...

In this paper, we show how beneficial effects of aging on static power consumption can be exploited to design reliable drowsy cache memories adopting dynamic voltage scaling (DVS) to reduce static power. First, we develop an analytical model allowing designers to evaluate the long-term threshold voltage degradation induced by bias temperature instability (BTI) in a drowsy cache memory. Through ...

This paper investigates the use of the guard traces to improve the Time-Domain Transmission (TDT) waveform and eye diagram for a flat spiral delay line. Two types of guard trace are adopted to implement and analysis in microstrip line and stripline structures. One is Two Grounded Vias type Guard Trace (TGVGT) and the other is Open-Stub type Guard Trace (OSGT). The timedomain analysis results by...

The increasing use of mixed signal circuits with analog and digital circuitry on the same lchip have created a set of demands that traditional circuit simuiators cannot meet very well. We pmsent techniques to efficiently handle the simulation of mixed signal analog/digital circuits, a d SYMPHONY , a fast mixed-signal simulator which embodies them. SYMPHONY combines a fast simulator for digital ...

Simultaneous switching noise (SSN) is a major cause of power integrity (PI) degradation that causes circuits to become unstable and experience errors. As modern ICs operate at higher speeds with higher density and lower voltages, SSN has become a serious issue that must be addressed to ensure system stability during the short riseand fall-times of the logic transient states. Most traditional de...

We investigate the -failure modes of a comb-drive surface-micromachined microresonator that are caused by particulate 'contaminations. The microresonator structure is chosen as our research vehicle because it pdssesses all the primitive components found in many capacitive-based MEMS sensors and actuators. Process simulation is used to create the full-spectrum of defective structures caused by f...

In this work, first an accurate model for I-V characteristics of sub-90-nm MOSFET in the linear and saturation regions is proposed. The model, which is intended for fast analytical calculation of the current, is based on the BSIM3v3 model. Instead of using constant Vth and VA voltages, as is assumed in the BSIM3v3 model, these voltages are defined as functions of the gate-source voltage. The ac...

In the current scenario, with the increasing integration densities, most system-on-chip designs are partitioned into multiple clock domains. In this paper, an asynchronous FIFO (First-in Firstout pipeline) design is employed as a data transfer interface between two independent clock domains. Since the clocks on the either sides of the FIFO run at a different speed, the task to ensure the correc...

Carbon Nanotube Field Effect Transistors (CNFETs) are being widely studied as the possible alternatives to the conventional silicon-MOSFETs. In this paper we have successfully designed the CNFET-based digital logic gates and compared them with the existing CMOS technology based logic gates. The designs are modeled using 32-nm technology for both CNFET and CMOS technology, using Stanford Univers...