Instruction delivery is a critical component for wide-issue processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and bandwidth are limited by instruction cache misses, multi-cycle instruction cache accesses, and target or direction mispredictions for control-flow operations. This paper introduces a block-aware ISA (BLISS) that helps a...

Modern instruction sets extend their load/store-instructions with cache hints, as an additional means to bridge the processor-memory speed gap. Cache hints are used to specify the cache level at which the data is likely to be found, as well as the cache level where the data is stored after accessing it. In order to improve a program’s cache behavior, the cache hint is selected based on the data...

The contributions of this paper are twofold. First, an automatic tool-based approach is described to bound worst-case data cache performance. The given approach works on fully optimized code, performs the analysis over the entire control ow of a program, detects and exploits both spatial and temporal locality within data references, produces results typically within a few seconds, and estimates...

The architects and circuit designers are increasingly care about the power aspect of microprocessors. The larger amount of built-in hardware is, the higher power the processors likely consume. Low power consumption is highly required not only for the processors driven by batteries but also for the powerful desktop or server processors whose the power budgets that over 100 Watts are not so uncom...

In bus-based SMPs, cache misses and bus traffic pose key obstacles to high performance. To overcome these problems, several techniques have been proposed. Cache prefetching, read snarfing, software-controlled updating, and cache injection reduce cache misses; migrate-on-dirty, adaptive migratory detection, load-exclusive instruction, and exclusive prefetching reduce invalidation bus traffic.

As technology scales down, leakage energy accounts for a greater proportion of total energy. Applying the drowsy technique to a cache, is regarded as one of the most efficient techniques for reducing leakage energy. However, it increases the Soft Error Rate (SER), thus, many researchers doubt the reliability of the drowsy technique. In this paper, we show several reasons why the instruction cac...

MIPS-X is a 32-bit RISC microprocessor implemented in a conservative 2-p m, two-level-metal, n-well CMOS technology. High performance is achieved by using a nonoverlapping two-phase 20-MHz clock and executing one instruction every cycle. To reduce its memory bandwidth requirements, MIPS-X includes a 2-kbyte on-chip instruction cache. This cache satisfies 90 percent of all instruction fetches, a...

In modern high performance microprocessors, there has been a trend toward increased superscalarity and deeper speculation to extract instruction level parallelism. As issue rates rise, more aggressive instruction fetch mechanisms are needed to be able to fetch multiple basic blocks in a given cycle. One such fetch mechanism that shows a great deal of promise is the trace cache, originally propo...

On chip caches in modern processors account for a sizable fraction of the dynamic and leakage power. Much of this power is wasted, required only because the memory cells farthest from the sense amplifiers in the cache must discharge a large capacitance on the bitlines. We reduce this capacitance by segmenting the memory cells along the bitlines, and turning off the segmenters to reduce the over...