In this paper, high speed carry skip adders for two different circuits were proposed. In the conventional structure of CSKA consists of a chain of ripple carry adder (RCA) block and 2:1 multiplexer. In the proposed structure, parallel prefix adder network is used to improve the speed and energy parameters. In addition to this the proposed structure called AND-OR-Invert (AOI) and OR-ANDInvert (O...

In this paper, interesting full adder circuits are reviewed and compared concerning speed, power consumption, and silicon area. A modified full adder is also investigated by combining hybrid logics, namely, pass transistor logic and branch based logic. This architecture uses two independent parts to generate SUM and carry signals. The results show that ultra low power evolution, very small prop...

Low power design has become one of the primary focuses in both analogue and digital VLSI circuits. Many power consumption techniques have come in existence and with that the low power design is also achieved by scaling supply voltage, considering sub-threshold region in this region thereby obtaining a minimum energy consumption which also suits for low operating frequencies. In this paper propo...

This paper presents low-power characteristics of adiabatic complementary pass-transistor logic (ACPL) using four-phase AC power supply. Adiabatic CPL circuits consist of pure NMOS transistors, use CPL blocks for evaluation and bootstrapped NMOS switches to eliminate non-adiabatic loss of output loads. In this paper, combinational circuit (4-bit ripple carry adder) and sequential circuit (4-bit ...

Low power VLSI circuits have become important criteria for designing the energy efficient electronic designs for high performance and portable devices .The multipliers are the main key structure for designing an energy efficient processor where a multiplier design decides the digital signal processors efficiency.Multiplier is the most commonly used circuit in the digital devices. Multiplication...

In this study, it was attempted to design a high-performance single-walled carbon nanotube (SWCNT) bundle interconnects in a full adder. For this purpose, the circuit performance was investigated using simulation in HSPICE software and considering the technology of 32-nm. Next, the effects of geometric parameters including the diameter of a nanotube, distance between nanotubes in a bundle, and ...

The increasing demand for the high fidelity portable devices has laid emphasis on the development of low power and high performance systems. In the next generation processors, the low power design has to be incorporated into fundamental computation units, such as multipliers. The characterization and optimization of such low power multipliers will aid in comparison and choice of multiplier modu...

Nowadays, there is a need to design microelectronic circuits which utilizes less energy and small area because of extensive growth of portable devices like laptops, digital watches and personal communication devices like mobile phones, and continuous shrinking of technology node. Many applications require circuits of high throughput, small area and consume ultra-low power. In this regard, this ...

This paper presents a design strategy of eliminating signal degradation for memristor ratioed logic (MRL) gates. Based on the strategy, a novel MRL-based one-bit full adder is proposed. The inverters in circuit can effectively eliminate the degradation and restore signal integrity. To evaluate the effectiveness of the proposed one-bit full adder, an eight-bit full adder is demonstrated as a stu...

This paper presents the design of low power and high speed circuit using a new CMOS logic family called feedthrough logic. FTL arithmetic circuits provides for smaller propagation time delay when compared with the standard CMOS technologies. The proposed circuit has very low dynamic power consumption and lower propagation delay compared to the recently proposed circuit techniques for the dynami...