The Silicon Physical Unclonable Function (SPUF) was first introduced by Devadas. The silicon PUF works on the basis of the variations in delays present in the gates as well as wires. The ring oscillator PUF is one of the implementation of SPUF. The ring oscillator requires one pair of ring oscillators for each output bit. So for collecting more number of output bits to acquire safe security lev...

The paper introduces a new technique for on-line checking of FPGA based Finite State Machines (FSMs). This technique is based on the architecture comprising two portions: a self-checking FSM and a separate totally self-checking (TSC) Sum-OfMinterms (SOM) based checker. Each of these portions is implemented as a combination of an Evolution block and an Execution block. For achieving the TSC prop...

In order to improve the bioavailability of lutein (LUT), a novel lutein-stevioside nanoparticle (LUT-STE) were prepared previously, but information about LUT-STE on protecting eye health was limited. This study investigated effect antioxidant activity H2O2-induced human retinal pigment epithelial cells (ARPE) cells. LUT and (final concentration 5 μg/mL) significantly enhan...

BACKGROUND The micturition reflex is under the tonic influence of suprapontine structures including the anteromedial frontal cortex, basal ganglia, and hypothalamus. However, there have been few reports about the role of the hypothalamus on the lower urinary tract (LUT) function in humans. OBJECTIVE To investigate LUT function in patients with pituitary adenomas. METHODS Urodynamic studies ...

BACKGROUND We investigated risk factors for lower urinary tract (LUT) dysfunction and LUT symptoms in patients who successfully underwent renal transplantation (RTX). MATERIAL AND METHODS Ninety-five patients (54 males and 41 females) undergoing RTX (median age: 45 years old) at Hokkaido University Hospital were included in this study. Uroflowmetry (UFM), postvoid residual urine volume (PVR),...

Programmable LUT cascades are used to evaluate multi-output Boolean functions. This paper shows several representations of multi-output functions and introduces a new decomposition algorithm applicable to these representations. The algorithm produces LUT cascades with the limited number of rails, which leads to significantly faster circuits and applicability to large designs. The experiment sho...

This paper represents a cycle-based logic simulation method using an LUT cascade emulator, where an LUT cascade consists of multiple-output LUTs (cells) connected in series. The LUT cascade emulator is an architecture that emulates LUT cascades. It has a control part, a memory for logic, and registers. It connects the memory to registers through a programmable interconnection circuit, and evalu...

— This paper presents a new method of digital adaptive predistortion for linearization of Power Amplifiers (PA) exhibiting memory effects. The predistorter (PD) device consists of a Look-Up-Table (LUT) gain followed by a codebook of filters addressed by the index of the LUT. The adaptation is derived from direct learning for the LUT gains and indirect learning for the filter coefficients. We co...

This brief demonstrates a new adaptive digital predistortion architecture particularly suited to mobile handset applications. The central idea is to build a lookup table (LUT) that directly captures the static compressive nonlinearity of the power amplifier (PA) and then insert this LUT into the feedback path of a ΔΣ modulator. The oversampled ΔΣ modulator automatically performs both the invers...

The FPGA (Field-Programmable Gate Array) has recently become the popular hardware and so-called LUTs (Look up Tables) are basic of FPGAs logic. For example, n-LUT is MOS pass transistors multiplexer 2n-1 which input data receive SRAM cells logic function configuration (user’s projects Truth Table). Address inputs LUT variables. Therefore, we get one n-arguments for actual configuration. To m fu...