This study examines the performance of sparsely-connected associative memory models built using a number of different connection strategies, applied to oneand two-dimensional topologies. Efficient patterns of connectivity are identified which yield high performance at relatively low wiring costs in both topologies. It is found that two-dimensional models are more tolerant of variations in conne...

introduction: previous studies have demonstrated that the &beta-adrenergic; receptor antagonist propranolol impairs fear memory reconsolidation in experimental animals. there are experimental parameters such as the age and the strength of memory that can interact with pharmacological manipulations of memory reconsolidation. in this study, we investigated the ability of the age and the strength ...

Single Input Change (SIC) testing has been proposed for robust path delay fault testing. In this letter a new Built-In Self Test (BIST) method for SIC vector generation is presented. The proposed method compares favourably to the previously proposed methods for SIC pattern generation with respect to hardware overhead and time required for completion of the test.

Reseeding is used to improve fault coverage in pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external tester. Besides its high cost, testing using automatic test equipment (ATE) makes it hard to test the circuit while in the system. In this paper, we present a technique for built-in reseeding. Our technique requires no storage for the seeds. The s...

A new inter-core BIST circuits for tri-state buffers: T-BIST mainly consists of simple circuits distributed in the relevant blocks. It can give an excellent test-coverage with a little additional hardware. Its configuration is not specified by each SoC structure, so, it is suitable for a general/reusable testable IP.

Built-In Self-Test for logic circuits or logic BIST is gaining popularity as an effective solution for the test cost, test quality, and test reuse problems. Logic BIST implements most of ATE functions on chip so that the test cost can be reduced through less test time, less tester memory requirement, or even a cheaper tester. Logic BIST applies a large number of test patterns so that more defec...