The sheer sizes of modern datasets are forcing data-structure designers to consider seriously both parallel construction and compactness. To achieve those goals we need to design a parallel algorithm with good scalability and with low memory consumption. An algorithm with good scalability improves its performance when the number of available cores increases, and an algorithm with low memory con...

introduction: the present post-eventual research study was conducted with the purpose of comparing the memory performance between two distinct groups of 50 healthy children and 50 attention deficit hyperactivity disorder (adhd) children (25 girls and 25 boys) in tehran with an age range of 10-12. methods: the whole students were selected through simple random sampling method and were assessed i...

objective: the aim of present research is to investigate the effects of neurofeedback on cognitive function with emphasis on memory. method: this study is an experimental study. for this reason using a stratified sampling procedure sample of 30 subjects in 2 groups of experimental and placebo was selected. investigated subjects were assessed with the wechsler memory scale in two stages (pretest...

Table 1: Comparison of sum of cluster densities for MDS Peeling+DPRP and for the best of 10 Density-FM runs. Results for avq.small benchmark using Density-FM would require many days of SPARC-10 time. Bounded Size Maximum Density Subhyper-graph (BMDS) problem : Given a hypergraph H(V; E) and an integer B, nd the subhypergraph of H with maximum density and size B. While MDS was polynomial time so...

This paper presents a new Fault Simulator architecture for RAM memories. The key features of the proposed tool are: 1) user-definable fault models, test algorithm, and memory architecture; 2) very fast simulation algorithm; 3) ability to compute the coverage of any provided test sequence w.r.t. a user-defined set of fault models, and to eliminate redundant operations; 4) assessment of the power...

Non-Volatile Random Access Memory (NVRAM) is a novel type of hardware that combines the benefits traditional persistent memory (persistency data over failures) and DRAM (fast random access). In this work, we describe an algorithm can be used to execute NVRAM programs recover system after failure while taking architecture real-world systems into account. Moreover, NVRAM-destined on commodity har...

We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using their existing hardware and software resources. To accommodate our proposed new test methodology, minor modifications should be applied to base processor within its test phase. That is, we modi...

low cost and reliable system. In this paper, we present the run-time behavior of contour tracing algorithms for processing large documents, in a contemporary workstation environment. The performance criteria examined are processing time, memory usage, and the number of page faults. A new contour tracing algorithm based on Capson's algorithm is proposed and it is compared with other algorithms. ...