The microprocessor architecture transition from multi-core to many-core will drive increased chip-to-chip I/O bandwidth demands at processor/memory interfaces and in multi-processor systems. Future architectures will require bandwidths of 200GB/s to 1.0TB/s and will bring about the era of tera-scale computing. To meet these bandwidth demands, traditional electrical interconnect techniques requi...

A simplified version of a RlSC microprocessor has been implemented with E/D MESFET DCFL in the Vitesse HGaAs II process. This chip was designed to drive the development of digital GaAs design automation tools. The processor architecture was modified to fit DCFL technology. The 60,500-transistor circuit executes a set of 29 basic instructions. It dissipates 11 W and operates at over 100 MHz. The...

Current trend of technology scaling makes it possible to put a huge number of transistors on a single die. While dynamic power consumption can benefit from technology scaling, static power consumption get worse, thus making the latter the dominant factor of power consumption in future microprocessor systems. As on-chip cache memories require the most part of chip area and number of transistors,...

Integration of the Hard Disk Controller (HOC) today has taken on an extensive amount of functionality. From the host interface, error correction code, disk sequencer, microprocessor(s), servo control logic, buffer controller, to the embedded memory, the HDC has become a true system on a chip. Depending on the product, embedded DRAM is used as buffering for data between the host and media and po...

The IBM POWER4 processor is a 174-milliontransistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multisite design team. This paper describes the circuit and phy...

Abstract This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results using VHDL. The arbiter exploits the advantage of a concurrency control instruction (Brk) provided by the micro-threaded microprocessor model to set the priority processor and move the circulated arbitration token at the m...

The circuit techniques used to implement a 600MHz, out-of-order, superscalar RISC Alpha microprocessor are described. Innovative logic and circuit design created a chip that attains 30+ SpecInt95 and 50+ SpecFP95, and supports a secondary cache bandwidth of 6.4GB/s. Microarchitectural techniques were used to optimize latencies and cycle time, while a variety of static and dynamic design methods...

The Soc (system on a chip) is a new form of embedded system, which integrates microprocessor, analog IP cores, digital IP core and memory (or off-chip memory controller interface) on a single chip. It is usually customized (CSIC) or a standard product for particular purposes (ASSP). It successfully integrate the hardware integrated circuits and embedded software, which can implement the compute...

The number of transistors on a chip plays the main role in increasing the speed and performance of a microprocessor; more transistors, more speed. Increasing the number of transistors will be limited due to the design complexity and density of transistors. This article aims to introduce a new approach to increasing the number of transistors on a chip. The basic idea is to construct two-layer cr...

1. Abstract Steady increases in CPU core speeds continue to extend the range of applications for computer-based solutions, resulting in the creation of ever more responsive systems. At these higher core speeds, on-chip cache architectures are used to prevent the CPU from stalling when accessing relatively slow off-chip memory. In normal operation, most fetch-execute cycles occur internally, gua...