This paper presents local shielding techniques applied to a half-bridge inverter leg with the aim reduce common mode (CM) current noise at converter's DC input. The research study is conducted for 650V Enhancement Gallium Nitride (GaN) power transistor switches. Main contributors of parasitic capacitances referred inverter-leg middle point node are identified. Then, solutions proposed CM emissi...

In this paper, we present a study on three-terminal ballistic junction and their applications to rectifiers and MUX/DEMUX. Rectifying effect is observed up to 94 GHz at room temperature. Although THz frequency performance has been demonstrated by Monte Carlo simulation, the high impedance of the nano-device combined with the parasitic capacitances is a limiting factor. © 2006 Published by Elsev...

High frequency DACs requiring an output buffer find a speed limitation in the overall input capacitive load of the buffer. This communication presents an active scheme for the compensation of such a load, including the parasitic capacitances coming from reversely biased junctions associated to analog switches. Computer simulations on a given architecture (10-bit DAC) show the effectiveness of t...

A characterization methodology to model interconnect capacitance for accurate circuit simulation is presented. The method utilizes a simple measurement scheme to measure inter-layer capacitances. The measured data is then used to tune a layout tool for accurate interconnect parasitic extraction. Results show good fit between simulated and measured ring oscillator speeds for a production 0.5μm, ...

In this paper, a power laterally-diffused metal-oxidesemiconductor field-effect transistor (LDMOSFET) on In0.53Ga0.47As is presented. The device utilizes a thicker field-oxide with low dielectric constant under the field-plate in order to achieve possible reduction in device capacitances and reduced-surface-field effect. Using 2D numerical simulations, performance of the proposed device is anal...

Role of winding shielding on the parasitic capacitances of transformer and common-mode (CM) noise is analyzed in details when considering the effects of the secondary side noise source. Based on the proposed model of CM noise, two novel techniques to cancel CM noise by balancing noise is given; experiment results show CM noise is greatly reduced when the techniques are adopted.

The bulk MOSFET scaling has recently encountered significant limitations, mainly related to the gate oxide (SiO2) leakage currents (Gusev et al., 2006; Taur et al., 1997), the large increase of parasitic short channel effects and the dramatic mobility reduction (Fischetti & Laux, 2001) due to highly doped Silicon substrates precisely used to reduce these short channel effects. Technological sol...

In this paper, we present a new, physically based 3-terminal model for diffused and ion-implanted resistors. The model accounts for the effects of geometry, temperature, and bias, and includes parasitic p-n junction diodes. The junction depletion capacitances are distributed to model high-frequency behavior accurately.

The article reports the extraction of DC characteristics and small signal parameters Non-uniform Si TFET with dual material source (NUTFET-DMS) at different frequencies followed by its reliability investigation. device is examined analysing: (1) impact presence interface trap charges, (2) temperature variation (200- 400 K). In analysis it has been observed that in case absence charges increase ...

From the history of power electronics, the technology improvements in power semiconductors have been the driving force for this problem. Moving from bipolar to MOSFET technology has greatly increased switching speed. For current semiconductor technology, very fast devices are available. For the power MOSFET used in front end application, they could be switched with mega hertz frequency range. T...