Late changes in silicon design (ECO) is a common although undesired practice. The need for ECO exists even in high-level design flows since bugs may occur in the specifications, in the compilation, or due to late specification changes. Esterel compilation deploys sequential optimization to improve delay and area of the netlist. This makes it harder to find in the netlist where manual changes sh...

With recent advances in reverse engineering, attackers can reconstruct a netlist to counterfeit chips by opening the die and scanning all layers of original chips. This relatively easy counterfeiting is made possible by the use of the standard simple clocking scheme where all combinational blocks function within one clock period. In this paper, we propose a method to invalidate the assumption t...

Phased Logic (PL) is a synthesis and mapping methodology that translates a standard synchronous gate-level netlist to a non-clocked netlist of special gates called phased logic gates [1][2][3]. In this paper the implementation of PL gates and the switched capacitance of phased logic systems is discussed. An analysis of the dynamic power consumption of a phased logic system reveals a major defic...

This paper addresses the problem of testing path delay faults in a microprocessor core using its instruction set. We propose to self-test a processor core by running an automatically synthesized test program which can achieve a high path delay fault coverage. This paper discusses the method and the prototype software framework for synthesizing such a test program. Based on the processor's instr...

A new, small, and optimized for low power processor core named SIRIUS has been developed, simulated, synthesized to a netlist and verified. From this netlist, containing only primitives like gates and flip-flops, a mapping to an ASIC or FPGA technology can easily be done with existing synthesizer tools, allowing very complex SOC designs with several blocks. Emulation via FPGA can be done on alr...

We report our current research in a computer assisted methodology for synthesizing regular array processors using the Alpha language and design environment. The design process starts from an algorithmic level description of the function and nishes with a netlist of an array processor which performs the speciied function. To illustrate the proposed approach, we present the design of an array pro...

In this paper, we propose a novel interconnect-aware pipeline synthesis system for array based reconfigurable architectures. The proposed system includes interconnect-aware pipeline scheduling, post-placement communication scheduling and others. The experiments on a number of real-life examples demonstrate usefulness of the proposed method. For scheduling, our proposed interconnectaware pipelin...

This paper describes a design flow for data-dominated embedded systems. We use The Mathworks’ Simulink environment for functional specification and algorithmic analysis. We developed a library of Simulink blocks, each parameterized by design choices such as implementation (software, analog or digital hardware, ) and numerical accuracy (resolution, S/N ratio). Each block is equipped with empiric...

Binary decision diagrams (BDD) have gained a wide acceptance as a mathematical model for representation and manipulation of Boolean functions in VLSI CAD. In this paper we consider a special kind of BDDs called Structurally Synthesized BDDs (SSBDDs), which have an important characteristic property of keeping information about circuit’s structure. Despite the fact that the SSBDD model itself is ...

In the last few years, several practitioners have proposed a wide range of approaches for reducing the implementation area of the AES in hardware. However, an area-throughput trade-off that undermines high-speed is not realistic for real-time cryptographic applications. In this manuscript, we explore how Genetic Algorithms (GAs) can be used for pipelining the AES substitution box based on compo...