This paper proposes a reconfigurable current steering digital to analog converter (DAC). The differential non-linearity error (DNL) of the DAC is estimated on-chip. This is used to reconfigure the switching sequence to get a lower integral nonlinearity error (INL). A 10 bit segmented DAC along with the associated circuits for DNL estimation was designed and fabricated using 0.35μm CMOS technolo...

Structural changes were the main focus of many studies in recent years. Changes which alter the socio-economic status of a nation from deprived and traditional nature to a developed and modern one. The main hypothesis of this study is that, the economic development does not occur through a regular flow of life (linear fashion), and without resilience, but it certainly needs to pass through a mo...

In the 1950s and 1960s, dc performance specifications such as integral nonlinearity, differential nonlinearity, monotonicity, no missing codes, gain error, offset error, and drift, etc., were primarily used to characterize data converters. These specifications were adequate during this era, because most early applications (with the exception of PCM and radar, for example) dealt with dc or low f...

In this paper, a high-resolution time-to-digital converter (TDC) based on a field programmable gate array (FPGA) device is proposed and tested. During the implementation, a new architecture of TDC is proposed which consists of a measurement matrix with 1024 units. The utilization of routing resources as the delay elements distinguishes the proposed design from other existing designs, which cont...

This paper proposes a digital calibration algorithm for a 2-stage cyclic analog-to-digital converter (ADC) with 12-bit resolution used in a 33-Mpixel 120-fps CMOS image sensor. A simulation was performed to verify the algorithm with the large values of errors that we set. Results showed that the maximum differential nonlinearity (DNL) was improved to 0.49 LSB from 4.5 LSB, and that the integral...

A time-interleaved ADC system is an effective way to implement a high-sampling-rate ADC with relatively slow circuits. In the system, several channel ADCs operate at interleaved sampling times as if they were effectively a single ADC operating at a much higher sampling rate. Mismatches among channel ADCs degrade SNR and SFDR of the ADC system as a whole, and the effects of offset, gain and band...

Inherent nonlinearities like, deadband, stiction and hysteresis in control valves degenerate plant performance. Valve stiction standouts as a more widely recognized reason for poor execution in control loops. Measurement of valve stiction is essential to maintain scheduling. For industrial scenarios, loss of execution due to nonlinearity in control valves is an imperative issue that should be t...

this paper studies the biswas-milovic equation with log law nonlinearity. thegausson solution is obtained by the ansatz method. subsequently, theconservation laws are derived and the conserved quantities are computed usingthe gausson solution.

here a posteriori error estimate for the numerical solution of nonlinear voltena- hammerstein equations is given. we present an error upper bound for nonlinear voltena-hammastein integral equations, in which the form of nonlinearity is algebraic and develop a posteriori error estimate for the recently proposed method of brunner for these problems (the implicitly linear collocation method).we al...