The pertinent choice of flip-flop topologies is an essential importance in the design of VLSI integrated circuits for high speed and high performance CMOS circuits. Understanding the suitability of flipflops and selecting the best topology for a given application is an important issueto fulfill the need of the design to satisfy low power and high performance circuit. This paper presents a wides...

Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause problems both with heat dissipation and with current spikes. Compacting scan vectors greatly increases the power dissipation for the vectors (generally the power becomes several times greater). The compacted scan vectors o...

In this paper Two Hybrid digital circuit design techniques are produced as Hybrid MultiThreshold CMOS complete stack technique and Hybrid Multi-Threshold CMOS partial stack technique for reducing the leakage power dissipation in mode transistion.Tri-modal switch are performance depends on these two techniques reduce the leakage power dissipation. These technique are implemented in the CADENCE v...

Yield, Reliability and Power Supply considerations motivate the need to minimize power dissipation during test application. Two techniques for minimizing power dissipation when tests are applied to static CMOS combinational circuits are proposed. They are: (i) Test set ordering; and (ii) Repetition of test vectors. We show that: although (i) is NP-Hard good heuristics can be developed; and an o...

Optimization of testing power is a major significant task to be carried out in digital circuit design. Low power VLSI circuits dissipate more power during testing when compared with that of normal operation. As the feature size is scaled down with process technology advancement, power minimization has become a serious problem for the designers as well as the test engineers. Test vector reorderi...

-In current scenario, VLSI circuit’s greatest challenges is to reduce the power dissipation and surface area so that longer life and high performance achieved to greater extent. The key parameter is threshold voltage to reduce the leakage power. In our proposal, we design low power and high performance JK flip-flop. JK flip-flop is designed with the help of D flip-flop and with some logic gates...

In this paper we discuss some aspects of designing arithmetic circuits with low power consumption. We focus on digit-serial processing techniques, as well as minimum adder multipliers, and multiple constant multiplication. A review of power dissipation sources in CMOS is given. Further, we discuss some methods to decrease the power dissipation of the algorithmic, arithmetic, and architecture le...

Field programmable gate arrays (FPGAs) have become an attractive implementation medium for digital circuits. FPGA design’s big challenge is to find a good trade-off between flexibility and performance in terms of power dissipation, area density, and delay. This paper presents a new cluster-based FPGA architecture combining mesh and hierarchical interconnect topologies. Based on experimental met...

As MOSFET sizes and wire widths become very small in recent years, in uence of resistive component of interconnects on the estimation of propagation delay and power dissipation can no longer be neglected. In this paper we present formulas of output waveform at driving point and short-circuit power dissipation for static CMOS logic gates driving a CRC load. By representing the short-circuit curr...

A tree growing technique is used here together with classical scheduling algorithms in order to improve the test concurrency having assigned power dissipation limits. First of all, the problem of unequal-length block-test scheduling under power dissipation constraints is modeled as a tree growing problem. Then a combination of list and force-directed scheduling algorithms is adapted to tackle i...