This paper describes a new design of low power 3-2 compressor circuit for high speed multipliers. Power consumption of proposed 3-2 compressor circuit varies from 0.355 nW to 1.6964 nW and delay varies from 2.0390 ns to 2.0224 ns. Further, power delay product of proposed circuit varies from 7.23×10 -18 (J) to 34.30×10 -18 (J) with varying supply voltage from 1.8V to 3.3V. The proposed compresso...

This paper proposes a realization of power factor function generator having an arbitrary base and power factor which are determined by the ratios of the currents provided from outside of the circuit. The circuit characteristics do not depend on any transistor parameters, temperature, and other environmental conditions. The circuit operation is based on current mode that has a capability of low ...

The paper presents a new quasi adiabatic logic family that uses two complementary split-level sinusoidal power supply clock for digital low power applications such as sensors. The proposed two-phase adiabatic static CMOS logic circuit (2PASCL) is using the principle of energy recovery and adiabatic switching. It has switching activity that is lower than dynamic logic and can be directly derived...

The basic idea of the circuit fault diagnosis method based on logic is to establish a computer expert database system first, connect GPIB interface card, and then each intelligent instrument through standard bus. Through connection tested object adapter object, test platform are formed. Based traditional simulation model, this paper improves switching power supply, designs model simulation, dea...

10kV linked SVG module power supply from their own h-bridge power, supply is unstable. To solve this problem, this paper proposes a new way to take power, using a combination of full-bridge push-pull circuit with isolation transformer to solve the logical drive power between the power module and the SVG device self-consistent problem. The paper detailed analysis of the working principle and cha...

This paper presents a new circuit arrangement for a current-mode Wheatstone bridge that is suitable for low-voltage integrated circuits implementation. Compared to the other proposed circuits, this circuit features severe reduction of the elements number, low supply voltage (1V) and low power consumption (<350uW). In addition, the circuit has favorable nonlinearity error (<0.35%), operate with ...

In this paper we propose two buffer circuits for footed domino logic circuit. It minimizes redundant switching at the output node. These circuits prevent propagation of precharge pulse to the output node during precharge phase which saves power consumption. Simulation is done using 0.18μm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circui...

supply voltage system where low supply gates may feed into high supply gates energy savings for benchmark circuits in comparison when level converters are not allowed. of a level shifter circuit having a structure to reduce fall and rise. input voltage levels prohibit the use of direct-gate drive circuits for high-side signal are linked by a level shift circuit that must tolerate the high-volta...

In this paper, a quadrature phase shifter is presented. Due to operation in current-mode, the proposed circuit provides a wide frequency response, a low supply voltage, low power consumption and electronic controllability. Thus, it is very suitable for use in portable and battery-powered equipment such as hearing aid instrument and wireless radio device. The proposed quadrature phase shifter co...

In this paper authors have presented a new approach to improve the performance of the glitch free cascadable adiabatic logic (GFCAL) circuit by replacing the triangular power supply with sinusoidal and trapezoidal power supplies (that control the charging and discharging of the capacitive load) and by sizing of transistors. A simulative investigation and performance analysis of proposed approac...