A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pipeline, instead of doing it in the decode stage as conventional schemes do. In this way, the register pressure is reduced and the processor can exploit more instruction-level parallelism. Delaying the allocation of phy...

The proposed Built-In Self-Diagnosis method (BISD) is based on the standard BIST architecture and can be integrated with recent, commercial DFT techniques, LP-TPG for in-field testing and in-field diagnostic data collection. To find maximum faults, structural diagnosis is used which does reveal the diagnostic information. A new low power test pattern generator using a linear feedback shift regi...

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It is well known that in an asynchronous message-passing system, one can emulate an atomic register providing that more than half of the processes are non-faulty. By contrast, when a majority of the processes may fail, simulating atomic register is not possible. This paper investigates weak variants of atomic registers that can be simulated tolerating a majority of processes failures. Specifica...