The Residue number system (RNS) is inherently suited to high speed computations using custom tailored VLSI systems. In this paper, an algorithm for residue addition, based on a novel, 'non unique' number representation scheme, is implemented by a systolic array embedded in a VLSI chip. The pipelined cells are implemented, using a true single phase clock dynamic circuit structure, with computer ...

The peak-to-average power (PAPR) is one of the main challenges in multicarrier transmissions. Aiming at reducing the PAPR, we propose a residue number system (RNS)-based OFDM parallel transmission scheme. The key idea of the proposed scheme is to utilize the parallel property of RNS to convert the input signals into the parallel smaller residue signals while utilizing the characteristic of RNS ...

The Residue Number System (RNS) is a non-weighted system that is very efficient in digital signal processing and communicational applications. The previous proposed methods for the residue to binary (R/B) conversions are based on the Chinese Reminder Theorem (CRT) or Mixed Radix Conversion (MRC). These theorems are difficult to implement. In this paper, we present a new highspeed ROM-less resid...

Execution of arithmetic operations at a very high speed in real time is the major concern in digital signal processing (DSP) because DSP algorithms are computation intensive. In recent times, Residue Number Systems (RNS) are considered as alternative to binary number system because of their capabilities of performing “carry-free” addition based on proper selection of the modulii set. Double Bas...

In low-power hardware implementations for classification algorithms, it is often essential to use physical resources efficiently. this sense, the of modulo-M integer operations instead floating-point arithmetic, can lead better performance, especially when M represents dynamic range an arithmetic block Residue Number System (RNS) [1,2]. Following premise, work aiming provide a methodology imple...

Multi-moduli architectures are very useful for reconfigurable digital processors and fault-tolerant systems that utilize the Residue Number System (RNS). In this paper we propose a novel architecture for configurable modulo 2±1 multipliers. It uses the modified Booth encoding of the input operand for deriving the required partial products and an adder tree followed by a sparse parallel-prefix f...

Residue generator is an essential building block of encoding/decoding circuitry for arithmetic error detecting codes and binary-to-residue number system (RNS) converter. In either case, a residue generator is an overhead for a system and as such it should be built with minimum amount of hardware and should not compromise the speed of a system. Multioperand modular adder (MOMA) is a computationa...

Third generation cellular network technology (3G) can revolutionize communications and data exchanges between many people in a more overwhelming fashion than 2G and 2.5G networks did. The 3G UMTS, the 3G GSM and the 3G GPRS rely on the KASUMI block cipher. Therefore, increasing speed, decreasing power consumption and error detection/correction are the major concerns of the KASUMI algorithm and ...

Over the centuries, information security has become a major issue. Encryption and decryption of data has recently been widely investigated and developed because there is a demand for a stronger encryption and decryption which is very hard for intrusion. Cryptography plays major roles in fulfilment of these demands. Many of researchers have proposed a lot of encryption and decryption algorithms....

The residue number system (RNS) is an integer system capable of supporting high speed concurrent arithmetic. One of the most important consideration when designing RNS system is reverse conversion. The reverse converter for recently proposed for the four-moduli set {2n −1,2n,2n +1,22n+1 −1} is based on new Chinese remainder theorems II (New CRT-II) [6]. This paper presents an alternative archit...