In this paper, a CMOS custom Integrated Circuit featuring a multi-stage Universal Switched-Capacitor (SC) Filter is Introduced. The network is based on the Generalized Immittance Converter (GIC) configuration, known for its excellent passive and active sensitivities. CMOS switches were used for elements relocation and are digitally controlled to select and realize different filter topologies. S...

This paper studies the design of an optimal relaxed causal sampler using sampled data system theory. A lifted frequency domain approach is used to obtain the existence conditions and the optimal sampler. A state space formulation of the results is also provided. The resulting optimal relaxed causal sampler is a cascade of a linear continuous time system followed by a generalized sampler and a d...

For a sampled-data control system, we propose to choose the time between samples to be shorter than the computational delay involved in computing the control signal, an approach we call intradelay sampling. It is shown that, utilising a parallel computing architecture, this is indeed feasible and that intra-delay sampling schemes yield better performance than their slower sampling counterparts.