A broadband digital harmonic vector voltmeter proposed previously and studied theoretically by the authors was implemented using a special-purpose, random sampling strategy, to avoid the bandwidth limitations due to the finite conversion time of the sample-and-hold and analog-to-digital-conversion (S/H-ADC) devices. The experimental results have shown that the bandwidth of the instrument is not...

This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. T...

Based on a conventional flash architecture a 4-bit GaAs analog to digital (A/D) converter has been designed using OMMIC-Philips GaAs foundry and particularly its commercial enhancement/depletion mode 0.18 μm pHEMT technology process. The ADC operates at 7.5 GHz sampling rate with full power analog input bandwidth from DC to Nyquist frequency. Differential source coupled FET logic (SCFL) was use...

We present low-complexity algorithms for transmitter and receiver front-end suited to the implementation of software defined radio (SDR) terminals. The proposed algorithms make the processing sampling frequency independent of the symbol rate of the digitally modulated signal and use the “IF-sampling” technique for D/A and A/D conversion. As a case-study, we consider a training-based joint multi...

One emerging trend of high-speed low-power ADC design is to leverage the successive approximation (SAR) topology. It has successfully advanced the power efficiency by orders of magnitude over the past decade. Given the nature of SAR algorithm, the conversion speed is intrinsically slow compared to other high-speed ADC architectures, and yet minimal static power is required due to the mostly dig...

This paper presents an architecture of signaldependent analog-to-digital converter (ADC) based on MINIMAX sampling scheme that allows achieving high data compression rate and power reduction. The proposed architecture consists of a conventional synchronous ADC, a timer and a peak detector, and AD conversion is carried out only when input signal peaks are detected. To improve the accuracy of sig...

One of the primary challenges in the development of the Advanced Receiver is the ability to accommodate a wide variety of possible data rates, motivated by the desire to support different missions for the Deep Space Network (DSN) under different adverse conditions. To conform to fixed architectures such as the analog-todigital converter (ADC) used at the front end and tracking loops used subseq...