Xilinx® devices are designed to have an inherently low susceptibility to single event upsets (SEUs). This application note provides a substantial discussion of strategies and representative calculations for handling SEUs with an emphasis on reliability when addressing these low probability events. This application note introduces an SEU controller macro that can be included in any Virtex®-5 FPG...

This paper presents a dual-modular-redundancy and dual-level error-interception based triple-node-upset (TNU) tolerant latch design (namely DDETT) for safety-critical applications. The DDETT comprises two parallel single-node-upset self-recoverable cells to store values three C-elements intercept errors. Both of the are constructed from triple mutually-feeding-back 2-input C-elements, feed inte...

Random Access Memory (RAM) refers to the main memory of a computer. For central processor unit (CPU) operate quickly and effectively, it stores operating system software, applications, other data. Unfortunately, single event upset high-soft error problems plague standard static RAM (SRAMs) in aircraft applications (SEU). Many Radiation-Hardened-Based Designs (RHBD) Radiation-Hardened-Polar (RHP...

Future technologies below 90nm will present transistors so small that they will be heavily influenced by electromagnetic noise and SEU induced errors. This way, together with process variability, design as known today is likely to change. Since many soft errors might appear at the same time, a different design approach must be taken. The use of stochastic computation operators as an inherently ...

Systems designed with FPGAs benefit from significant improvements over ASICS, such as rapid-process technology scaling and design innovation, which permit the use of FPGAs in high-availability, high-reliability, and safety-critical systems. However, along with technology scaling come other effects such as increased susceptibility to soft errors that previously could be ignored. These soft error...

This article describes how to analyse radiation-induced effects using traditional RF metrics in Radio Frequency Integrated Circuits (RFIC) be used the implementation of Software-Defined (SDR). The impact Total Ionizing Dose (TID) and Single Event Effects (SEE) on device characteristics are shown their consequences for a SDR discussed. analysis is based Error Vector Magnitude (EVM), Carrier Offs...

This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs. First, a cost and double-node-upset (DNU) completely (LCDNUT) design is proposed. The mainly comprises storage module (SM) feeding back to 3-input C-element. SM consists of eight input-split inverters. Since the inputs C-element cannot be simultaneously flipped, tolerates any DNU in SM. When single node...

Single Event Upsets (SEU) arising from atmospheric neutrons and alpha particles are becoming increasingly important in combinational logic circuits. Combinational logic is resilient to soft errors due to three masking phenomena: (1) Logical Masking, (2) Electrical Masking, and (3) Latching-window Masking. This paper concentrates on logical masking, and proposes a probabilistic model which calcu...

In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are proposed and evaluated. The proposed radiation hardened SRAM cells are capable of fully tolerating single event upsets (SEUs). Moreover, they show a high degree of robustness against single event multiple upsets (SEMUs). Over the previous SRAM cells, RATF1 and RATF2 offer lower area and power overhead. The H...