Recently, the soft error rates of integrated circuits is increased by process scaling. Soft error decreases the tolerance of VLSIs. Charge sharing and bipolar effect become dominant when a particle hit on latches and flip-flop. soft error makes circuit more sensitive to Multiple Cell Upset (MCU). We analyze the MCU tolerance of redundant latches in 65 nm process by device simulation and particl...

We measure distributions of heavy-ioninduced Single Event Transient (SET) pulse widths from the 4 kinds of inverter chains to measure their characteristics and estimate SET-induced soft error rates on a Flip-Flop (FF) and a delayed TMR FF. Test chip was fabricated in 65-nm bulk CMOS process and measurement results show that maximum SETinduced soft error rate on a FF is equivalent to 20% of Sing...

Control circuit in an asynchronous design is comprised mostly of Muller C-elements. Previous work has concentrated on power, performance, and area issues of various CMOS implementations of the C-element. In this paper we carried out a thorough soft error analysis of four popular CMOS implementations of the Muller C-element. It shows that SIL implementation has the best soft error resilience. Op...

SRAM-based FPGAs are increasingly becoming more popular in applications where high dependability, low cost, and fast time-tomarket are important constraints. However, these devices are more susceptible to single-event upsets (SEUs) compared ASIC designs. The error models of SRAM-based due to SEUs are more complicated than those of ASICs since soft-errors in the configuration memory result in pe...

In 1998 May, the soft gamma repeater SGR1900+14 emerged from several years of quiescence and emit a series of intense bursts, one with a time history unlike any previously observed from this source. Triangulation using Ulysses , BATSE, and KONUS data give a 1.6 square arcminute error box near the galactic supernova remnant G42.8+0.6. This error box contains a quiescent soft X-ray source which i...

Glitches due to the secondary neutron particles from cosmic rays cause soft errors in integrated circuits (IC) that are becoming a major threat in modern sub 45nm ICs. Therefore, researchers have developed many techniques to mitigate the soft errors and some of them utilize the built in error detection schemes of low-power asynchronous null conventional logic (NCL). However, it requires extensi...

the critical charge by increasing the gate capacitance while errors are gaining importance as technology scales. Flip-flops, an important component of pipelined architectures, are becoming more susceptible to soft errors. This work analyzes soft error rates on a variety of flip-flops. The analysis was performed by implementing and simulating the various designs in 70 nm, 1V CMOS technology. Fir...

The generalization properties of support vector machines (SVMs) are examined. From a geometrical point of view, the estimated parameter of an SVM is the one nearest the origin in the convex hull formed with given examples. Since introducing soft margins is equivalent to reducing the convex hull of the examples, an SVM with soft margins has a different learning curve from the original. In this p...

The soft error rates (SER) in logic circuits increase quickly as devices scale. Existing techniques to mitigate soft errors in logic circuits often incur large overheads. In this work, we propose a ’lightweight’ technique that detects soft errors in logic circuits, utilizing the concept of temporal sampling. The technique adds some modifications to the conventional pipeline to allow data to be ...

Three different latch structures are fabricated in a 65 nm FDSOI process. We evaluate soft-error tolerance of latches by device simulations and α particle, neutron, heavyion irradiation tests in order to identify which transistor type is dominant to cause soft errors. The latch structure including an inverter with stacked NMOS and unstacked PMOS transistors has enough tolerance against soft err...