Among various testing methodologies, Built-in SelfTest (BIST) is recognized as a low cost, effective paradigm. Also, full adders are one of the basic building blocks of most arithmetic circuits in all processing units. In this paper, an optimized testable 2bit full adder as a test building block is proposed. Then, a BIST procedure is introduced to scale up the building block and to generate a s...

Real-time on-chip measurement of bit error rate (BER) for high-speed analog-to-digital converters (ADCs) does not only require expensive multi-port high-speed data acquisition equipment but also enormous post-processing. This paper proposes a low-cost built-in-self-test (BIST) circuit for high-speed ADC BER test. Conventionally, the calculation of BER requires a high-speed adder. The presented ...

Most approaches to the synthesis of built-in self test (BIST) circuitry use a manual choose-and-evaluate approach, where a particular BIST generator is chosen and then evaluated by faultsimulating the design with the vectors that the chosen generator generates. We develop an algorithmic synthesis-during-test approach in this paper, wherein the tasks of synthesizing the BIST logic and directed t...

A new microcode-based BIST(Built-In Self Test) circuitry for embedded memory components is proposed in this paper. The memory BIST implements march algorithms which are slightly modified by adopting DOF(Degree of Freedom) concept to detect ADOFs(Address Decoder Open Faults) on top of conventional stuck faults. Furthermore it is shown that the march BIST modified can capture a few NPSFs(Neighbor...

When stuck-at faults are targeted, scan design reduces the complexity of the test problem. But for delay fault testing, the standard scan structures are not so efficient, because delay fault testing requires the application of dedicated consecutive two-pattern tests. In a standard scan environment, pre-determined two pattern tests cannot be applied to the circuit under test because of the seria...

On-chip Built-In Self-Test (BIST) based diagnosis of the embedded Field Programmable Gate Array (FPGA) core in a generic System-on-Chip (SoC) is presented. In this approach, the embedded processor core in the SoC is used for reconfiguration of the FPGA core for BIST, initiating the BIST sequence, retrieving the BIST results, and for performing diagnosis of faulty programmable logic blocks, memo...

This work presents an efficient on-chip ramp generator targeting to facilitate the deployment of Built-In Self-Test (BIST) techniques for ADC static linearity characterization. The proposed ramp generator is based on a fully-differential switched-capacitor integrator that is conveniently modified to produce a very small integration gain, such that the ramp step size is a small fraction of the L...

In this paper, a built-in self-test (BIST) procedure is proposed for testing and fault tolerance of molecular electronicsbased nanofabrics. The nanofabrics are assumed to include up to 10 devices/cm; this requires new test strategies that can efficiently test and diagnose the nanofabrics in a reasonable time. Our BIST procedure utilizes nanofabric components as small test groups containing test...

We present stuck-at and bridging fault simulation results for previously proposed Built-In Self-Test (BIST) approaches for the programmable interconnect resources in Field Programmable Gate Arrays (FPGAs). In addition, new BIST approaches are proposed and analyzed via fault simulation. The fault simulation results are used to compare and evaluate the fault detection capabilities and effectivene...

The chief goal of partial scan/BIST selection is to identify the minimum number of flip flops in a design which can be converted into test flip flops to enable high fault coverage. We propose the elimination of reconvergent fanout during partial scan/BIST selection by choosing flip flops on reconvergent fanout paths. We present a partial scan/BIST selection algorithm which minimizes reconvergen...