This paper describes team Turing’s submission to SemEval 2017 RumourEval: Determining rumour veracity and support for rumours (SemEval 2017 Task 8, Subtask A). Subtask A addresses the challenge of rumour stance classification, which involves identifying the attitude of Twitter users towards the truthfulness of the rumour they are discussing. Stance classification is considered to be an importan...

In this article we present test and verification challenges for system chips that utilize on-chip networks. These SOCs and networks on a chip are introduced, where the NOC is exemplified by Philips’ ÆTHEREAL NOC architecture. We discuss existing test and verification methods for SOCs and NOCs, and show the particular advantages of using an NOC for both testing and verifying the network, and tes...

of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy COVERAGE-DRIVEN TEST GENERATION FOR FUNCTIONAL VALIDATION OF PIPELINED PROCESSORS By Heon-Mo Koo December 2007 Chair: Prabhat Mishra Major: Computer Engineering Functional verification of microprocessors is one of the most complex and ex...

In This paper presents an overview of a state-of-the-art text-independent speaker verification system. First, an introduction proposes a modular scheme of the training and test phases of a speaker verification system. Then, the most commonly speech parameterization used in speaker verification, namely, cepstral analysis, is detailed. Gaussian mixture modeling, which is the speaker modeling tech...

Verification bias arises in diagnostic test evaluation studies when the results from a first test are verified by a reference test only in a non-representative subsample of the original study subjects. This occurs, for example, when inclusion probabilities for the subsample depend on first-stage results and/or on a covariate related to disease status. Reference standard bias arises when the ref...

Design reuse and verification reuse are important to satisfy time to-market requirements. Designer must be able to reuse Intellectual Property in the design as golden model. Reuse of verification environment across different designs of the domain saves time to market further and improves total design verification quality. The Physical Layer is a fundamental layer upon which all higher level fun...

This paper describes a test-bed for verification and validation activities in KT-NeOSS (Korea Telecom New Operations Support System) development. In this paper, we show the test phases for performing verification and validation activities during the development and maintenance of KT-NeOSS. We describe the experiences and considerations in building the test-bed for the activities. With this test...

83 NEC TECHNICAL JOURNAL Vol.1 No.1/2006 Our Systems Solutions Division had previously developed V-TEST (Verification Tool for Embedded SysTems), which later became the basis of V-TEST for FlexRay. V-TEST was a tool for improving the efficiency of verification of the hardware/software coordination of embedded systems as well as of the systems themselves. In the following we would like to begin ...

Software is used in many safetyand security-critical systems. Software development is, however, an error-prone task where a software developer tries to precisely formalize in a programming language their imprecise ideas about a program. Formal methods help to reduce this problem. These methods add another layer to the software development allowing to formalize and to check desired properties of...