Advancements in parallel and cluster computing have made many complex Monte Carlo simulations possible in the past several years. Unfortunately, cluster computers are large, expensive, and still not fast enough to make Monte Carlo useful for calculations requiring a near real time evaluation period. For Monte Carlo simulations, a small computational unit called a Field Programmable Gate Array (...

Recent advances in FPGA technologies allow to configure the RAM-based FPGA devices in a reduced time as an effective support for real-time applications. The physical dimensions of FPGAs (pinout and gate count) limit the complexity of circuits that can be implemented. In many applications, very large circuits should be realized without requiring either a very large FPGA or many FPGAs; in some re...

In this paper a state-of-the-art FPGA (Field Programmable Gate Array) based high speed parallel signal processing system (SPS) for adaptive optics (AO) testbed with 1 kHz wavefront error (WFE) correction frequency is reported. The AO testbed consists of Shack-Hartmann sensor (SHS) and deformable mirror (DM), tip-tilt sensor (TTS), tip-tilt mirror (TTM) and an FPGA-based high performance SPS to ...

reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements, increased performance, and increased functionality. However, since leveraging these additional benefits requires specific designer expertise, which increases design time, PR has not yet gained widespread usage. Even though ...

Abstract— This paper presents an efficient method to design & implement WCDMA based digital up converter for Software Radios. The Park McClellan algorithm has been proposed for optimal filter length to reduce hardware requirements. A computationally efficient polyphase decomposition structure is also proposed to optimize both speed and area. The embedded multipliers and LUTs of target FPGA are ...

This new toolchain for accelerating application on CPU-FPGA platforms, called Courier-FPGA, extracts runtime information from a running target binary, and re-constructs the function call graph including input-output data. Then, it synthesizes hardware modules on the FPGA and makes software functions on CPU by using Pipeline Generator. The Pipeline Generator also builds a pipeline control progra...

For FPGA-based scientific simulation systems, hardware design technique that can reduce required amount of hardware resources is a key issue, since the size of simulation target is often limited by the size of the FPGA. Focusing on FPGA-based biochemical simulation, this paper proposes hardware design methodology which finds and combines common datapath for similar rate law functions appeared i...

In this paper an efficient multiplier based approach is presented to implement digital up converter for Software Defined Radio based GSM applications. The proposed DUC design has been implemented by hybridizing the multiplier based and multiplier less techniques. The concept of polyphase decomposition technique has been used to map the design on multiplier based FPGA. The speed performance has ...