IS design today is driven primarily by technical and functional requirements, and the economic implications for design are not yet well understood. This study argues that system design and architecture must reflect assessments of economic trade-offs besides satisfying technical/functional requirements. Modeling the economic performance structure behind IS design can highlight these trade-offs a...

ARM single-ISA heterogeneous multicore processors combine high-performance big cores with power-efficient small cores. They aim at achieving a suitable balance between performance and energy. However, a main challenge is to program such architectures so as to efficiently exploit their features. In this paper, we study the impact on performance and energy trade-offs of single-ISA architecture ac...

This paper demonstrates thatcompositionand refinement techniques are a promising solution for performing rigorous, security architecture trade-off analysis. Such analysis typically occurs in one of two forms: comparing two architectures for implementation and determining the impact of change to an implemented architecture. Composition and refinement techniques reduce the overhead of such analys...

In this paper we propose an on-line self-test architecture for hardware implementations of Advanced Encryption Standard (AES). The solution assumes a parallel architecture and exploits the inherent spatial replications of this implementation. Because Substitution boxes (S-Box) represent the largest hardware in this architecture, we focus on faults affecting these S-Boxes and propose a trade-off...

Methods to insure that an architecture meets its intended requirements are important, especially when performing architectures analysis, requirement generation, trade-offs with alternate architectures, and reviews and verifications of designs. One such approach is to use methods that focus on system attributes. The key to success in this approach is to understand which system attributes should ...

The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system. Thus, performances of pointer-based and sparse-matrix computations as well as multimedia applications are significantly enhanced. A key feature of the DIVA architectu...

A novel low-complexity scalable and systolic dual basis multiplier over GF(2 ) m is proposed in this paper. It is derived by utilizing the block Hankel matrixvector representation and is suitable for finite fields generated by irreducible trinomials. The proposed scalable architecture can achieve good trade-off between throughout performance and hardware complexity for implementing cryptographi...

A new GF(p) cryptographic processor architecture for elliptic curve encryption/decryption is proposed in this paper. The architecture takes advantage of projective coordinates to convert GF(p) inversion needed in elliptic point operations into several multiplication steps. Unlike existing sequential designs, we show that projecting into (X/Z,Y/Z) leads to a much better improved performance than...

— This paper presents a family of architectures for FFT implementation based on the decomposition of the perfect shuffle permutation, which can be designed with variable number of processing elements. This provides designers with a trade-off choice of speed vs. complexity (cost and area.). Hardware comparison to other existing pipeline architecture presented based on implementation of 1024-poin...