Formal tools for the verification of HDL synchronous descriptions are currently in development for both the Verilog [2,3] and VHDL languages [1], but little work has been done on tools able to handle both languages [8]. The well known reason is that VHDL and Verilog's simulation semantics are quite different. So, the task of deciding formally whether two synchronous descriptions written in the ...

A design step transforms a specification into an implementation and may take place on several levels of abstraction. If we want to formally capture the design step in order to reason about its correctness we need on the one hand formal VHDL semantics capturing the static and dynamic aspects of the VHDL simulation model. On the other hand, we need special purpose semantics supporting the use of ...

This paper describes a methodology for top-down design, modeling, and simulation of complete π/4 DQPSK system using hardware description language VHDL-AMS. Two system implementations are considered: with and without Viterbi encoder/decoder. VHDL-AMS implementations of various RF blocks (e.g. a realistic channel model) are developed, the system is simulated, and bit error rate is evaluated in th...

A methodology for modifying VHDL descriptions is the core of this paper. Modifications are performed on general RTL descriptions composed of a mix of control and computation, that is, the typical type of description used for designing at the RT level. Such VHDL descriptions are automatically partitioned into a reference model composed of a controller driving a data-path. We call this transforma...

The aim of this paper is to present an approach that allows the generation of VHDL from system level specifications in SDL. Our approach overcome the main known problem encountered by previous work which is the communication between different processes. We allow SDL communication to be translated into VHDL for synthesis. This is made possible by the use of an intermediate form that support a po...

17 to their colleagues of CHARME for many helpful discussions and friendly cooperation over many years. 16 Many research groups have proposed formal semantics for VHDL, to apply formal verification techniques on designs described in that language. The FSM model for clock synchronized circuits closest to ours is Bull's [15], but currently only machines with identical state encodings can be compa...

A simple formal semantics for the standard hardware description language vhdl is set out in functional style. The presentation comprises an executable speci-cation for a synchronously clocked vhdl simulator.