This paper develops an instruction-level loop scheduling technique to reduce both execution time and bus switching activities for applications with loops on VLIW architectures. We propose an algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), to minimize both schedule length and switching activities for applications with loops. In the algorithm, we obtain the best schedule from ...

In this document the Instruction Set Architecture (ASI) simulation issue is discussed. Typical tradeoffs between Flexibility, Speed and Accuracy are shown. Based on hypothesis on Architecture approach (VLIW) and Applications of interest (DSP and Multimedia), this article presents a solution representing a challenging compromise in ASI simulation. A fast, accurate and flexible ASI simulation env...

The Parallel Architecture Core (PAC) is a new VLIW DSP architecture, featuring a two cluster design, and partitioned, distributed register files with restricted access ports. Such an irregular processor poses many challenges in the construction of its compiler. This paper presents our work in providing the compilation support for PAC, based on the Open Research Compiler (ORC). We describe the d...

This paper introduces Simultaneous Multi-Processor (SMP) cores. These SMP cores offer a high performance, efficient application target for the embedded system developer. SMP cores can be reprogrammed like a microprocessor in response to application requirement changes. They do not require caching, or superscalar instruction processing, greatly reducing silicon size and energy consumption. Also ...

ÐThis paper presents a novel software pipelining approach, which is called Swing Modulo Scheduling (SMS). It generates schedules that are near optimal in terms of initiation interval, register requirements, and stage count. Swing Modulo Scheduling is a heuristic approach that has a low computational cost. This paper first describes the technique and evaluates it for the Perfect Club benchmark s...

Recent studies have shown that the ability of disambiguating memory addresses (often referred to as alias analysis) gives concrete performance benefits to the compilation of C code for VLIW machines. This experimental research studies which factors, though external to alias analysis, strongly determine its impact on the performance of compiled code. These factors belong to two categories: archi...

Interleaved multithreading is a technique in which the processor starts executing a different task when the current thread is stalled. However, whereas different forms of hardware multithreading have been extensively evaluated in superscalar processors, an evaluation of multithreading techniques in a VLIW architecture is frequently missing. The objective of this paper is to determine an efficie...

The design of high-performance application-specific multi-core processor systems still is a time consuming task which involves many manual steps and decisions that need to be performed by experienced design engineers. The ASAM project sought to change this by proposing an automatic architecture synthesis and mapping flow aimed at the design of such application specific instruction-set processor...

As technology scaling approaches to the nanometer, leakage power has become a significant component of the total power consumption. In this paper, we develop a novel leakage-aware modulo scheduling algorithm to achieve leakage energy savings for DSP applications with loops on VLIW architecture. The proposed algorithm is designed to maximize the idleness of function units integrating with leakag...

Data dependence analysis (DDA) on assembly code is a frequent problem in compilers and program analysis tools. The fundamentals of a DDA on code for simple processors are well understood. We propose a DDA method, that is applicable for a wider range of processors. This includes VLIW processors and processors with delayed branches and delayed register accesses. For these architectures, the instr...