In-memory computing using emerging technologies such as resistive random-access memory (ReRAM) addresses the ‘von Neumann bottleneck’ and strengthens present research impetus to overcome wall. While many methods have been recently proposed implement Boolean logic in memory, latency of arithmetic circuits (adders consequently multipliers) implemented a sequence operations increases greatly with ...

In this paper different low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 250MHz and 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed which are Array multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multipl...

Modulo multiplication plays an important role in the Fermat number transform and residue number systems; the diminished-1 representation of numbers has been found most suitable for representing the elements of the rings. Existing algorithms for modulo multiplication either use recursive modulo addition, or a regular binary multiplication integrated with the modulo reduction operation. Although ...

In this paper, a novel implementation of 8x8 Multiplier using 4-2 Compressors is presented; which produces quick results, especially for use in Digital Signal Processors and in Microprocessors. This multiplier uses a new partial-product reduction format which consecutively reduces the maximum output delay. The new design of multiplier requires less number of MOSFET’s compared to Wallace Tree Mu...

RISC architecture is used across a wide range of platforms from Cellular phones to super computers.In this paper,a 16bit RISC processor is designed, which utilizes minimum functional units without compromising in performance. The design is based on architectural modification made in the incrementer circuit which is used in program counter.A Low Power Area Efficient carry select adder and a high...

We designed reconfigurable 8x8 multiplier architecture in 180nm with 1.8 power supply based on Wallace Tree, efficient in power and regularity without increase in delay and area. The idea is the generation of partial products in parallel using AND gates. The addition of partial products is reducing using Wallace Tree which is hierarchically divided into levels. Therefore there will be a signifi...

Design of a high performance and high-density multiplier is presented. This multiplier is constructed by using the Wallace tree structure with pipelining. A fast carry select adder is used for the final two-operand adder. It is shown that the time delay for the entire multiplier is O(log(n)). The design is particularly carried out for a 32-bit multiplier with two sections of pipelining, to bala...

This paper describes the comparison of VLSI architectures on the basis of Speed, Area and Power of different type of Adders like Carry Chain Adder, Carry Look Ahead Adder, Carry Skip Adder, and Carry Select Adder and 32-bit pipelined Booth Wallace MAC Unit with Carry Chain Adder, Carry Look Ahead Adder, Carry Skip Adder, and Carry Select Adder is designed in which the multiplication is done usi...