Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital...

In nanotechnologies, quantum-dot cellular automata (QCA) offer promising and attractive features for nano-scale computing. QCA effectively overcomes the scaling shortfalls of CMOS technology. One of the variants of QCA is 4 Dot 2 Electron QCA which is well explored and researched. The main concentration of this study is on 2 Dot 1 Electron QCA, an emerging variant of QCA. A novel and efficient ...

This study introduces an optical DNA-based logic circuit that mimics a half-subtractor. The system contains an Au-surface immobilized molecular-beacon molecule that serves as a dual-gate molecule and outputs two series of fluorescence signals following Boolean INH and XOR patterns after interacting with one or two single-stranded DNA molecules as input. To the best of our knowledge, the system ...

Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to transistor leakage of low-order and high-order basic logic gates. The NAND and NOR gates have been designed using different design styles and circuit topologies, including complementary CMOS, partitioned logic and complem...

Two-dimensional (2D) technology computer-aided design (TCAD) is used to analyze and compare the multi-gate digital performance of the screen-grid field effect transistor (SGrFET) with a finFET. The switching speed of the all-n-type inverter is ten times faster for the n-SGrFET than for the n-finFET, while the noise margins are ∼400 mV for a 1 V supply for both devices. The performance of the co...

This paper compares two different logic styles based on 45 nm technology for implementing logic gates of upto two inputs in terms of their layout area, delay and power dissipation. The XOR gate has been implemented & designed using CMOS & Pass Transistor logic on 45 nm technology .The schematic of proposed gate has been designed & simulated by using DSCH3& its equivalent layout has been develop...