Proton-gated channels expressed by sensory neurons are of particular interest because low pH causes pain. Two proton-gated channels, acid-sensing ionic channel (ASIC) and dorsal root ASIC (DRASIC), that are members of the amiloride-sensitive ENaC/Degenerin family are known to be expressed by sensory neurons. Here, we describe the cloning and characterization of an ASIC splice variant, ASIC-beta...

Many ASIC companies make it easy to add a PLL, offering the core as a drop-in cell on a standard-cell design or as a cell option in a gate array. However, that seemingly simple addition of a PLL cell to an all-digital ASIC can cause several problems if the ASIC designer isn’t careful. Although much of what is inside a PLL circuit is high-speed digital circuitry, the guts of the PLL include anal...

5 ASIC Technologies 8 5.1 Full Custom Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Standard Cell ASIC Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 Gate Array ASIC Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 Sea-of-Gates ASIC Technology . . . . . . . . . . . ....

For the Pre-Processor System of the ATLAS Level-1 Calorimeter Trigger we have built a fast signal-processing and readout ASIC (PPrAsic). The novel ASIC design environment incorporates algorithm development with digital hardware synthesis and verification. The purely digital ASIC was designed in Verilog HDL (hardware description language) and embedded in a system wide analog and digital simulati...

BACKGROUND Anxiety sensitivity is a useful construct in explaining anxiety disorders. The Anxiety Sensitivity Index for Children (ASIC) is a brief self-report designed to assess anxiety sensitivity in youth. METHOD Students (N = 1348; ages 10-17) completed a Spanish translation of the ASIC and measures of anxiety and depression. RESULTS Confirmatory factor analyses found that scores on the ...

Spartan FPGAs are an exciting, new alternative for implementing digital designs that, previously, would have employed ASIC 1 technology. Pre-existing ASIC intellectual property 2 can be adapted for use with Spartan devices by following a straightforward procedure. Each step of the pro-1. For the purposes of this application note, ASIC refers to mask gate array. 2. The term intellectual property...