To control the exponential growth of malware files, security analysts pursue dynamic approaches that automatically identify and analyze malicious software samples. Obfuscation and polymorphism employed by malwares make it difficult for signature-based systems to detect sophisticated malware files. The dynamic analysis or run-time behavior provides a better technique to identify the threat. In t...

Several manufacturers have recently announced the first simultaneous-multithreaded processors, both as single CPUs and as components of multi-CPU chips. All are small scale, comprising only two to four thread contexts. A significant impediment to the construction of larger-scale SMTs is the register file size required by a large number of contexts. This paper introduces and evaluates minithread...

Intel Itanium processors were designed with an on chip register stack engine (RSE) in order to reduce the overhead related to procedure call boundaries. The RSE automatically preserves values stored in stacked registers across procedure invocations. This architecture model significantly reduces the amount of spill code necessary to maintain an application’s state, which in turn reduces memory t...

Many techniques for increasing the amount of instruction-level parallelism (ILP) put increased pressure on the registers inside a CPU. These techniques allow for more operations to occur simultaneously at the cost of requiring more registers to hold the operands and results of those operations, and importantly, more ports on the register banks to allow for concurrent access to the data. One app...

Two algorithms that combine the operations of scheduling and recovery point insertion for high-level synthesis of recoverable microarchitectures are presented. The first uses a prioritized cost function in which functional unit cost is minimized first and register cost second. The second algorithm minimizes a weighted sum of functional unit and register costs. Both algorithms are optimal accord...

This paper represents the combination of Reduced Instruction Set Computer (RISC) system using VHDL and implement. This paper presents a RISC processor designing to achieve various arithmetic operations. The RISC is a 20 bit processor. KeywordsArithmetic Logic(AL), Central Processing Unit(CPU), Control Unit(CU), Field Programmable Logic Array(FPGA), General Purpose Register(GPR), Program Counter...

We propose a design of a 16-bit RISC CPU core using an adiabatic logic which is called a two phase drive adiabatic dynamic CMOS logic (2PADCL), in this paper. The proposed adiabatic RISC CPU is non-pipelined with a latency of three cycles, and also consists of six blocks; an arithmetic and logic unit (ALU), a program counter, a register file, an instruction decoder unit, a multiplexer and a clo...