Two general crossbar switch models are proposed: the modified one-sided crossbar switch and the ripple K one-sided crossbar switch. They both balance cost and reliability, where cost is expressed in terms of crosspoint count or area. The two-sided crossbar switch and the one-sided crossbar switch are two cases of these structures. These structures provide choices for compromising structures bet...

Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC performance is influenced by the router crossbar switch. This paper presents implementation of 10x10...

A wide-band crossbar switch configured as a non-blocking signal router can be used in various applications that need reconfigurable digital or analog cross connections such as network switches, CPU-memory connecting modules and wide tuning range radar switches. Current mode logic using IBM 8HP SiGe heterojunction bipolar transistors having fTs of 210 GHz and a symmetrical signal path design are...

This paper describes various aspects and implementaions of the crossbar interconnect. The performance of a multiprocessor system depends on having an efficient bus architecture. In System-on-a-Chip (SoC) there are different architecture types such as single stage networks, multi-stage networks, omega networks and crossbar networks. This paper focuses on the latter, the crossbar network. Most mo...

Network-on-Chip (NOC) has been proposed as an attractive alternative to traditional dedicated wire to achieve high performance and modularity. Power and Area efficiency is the most important concern in NOC design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC ...

Rapid growth of Internet traffic causes a new challenge in the design of high-speed switches. One of main design issues for high-speed switches is a scalability problem. This paper proposes a scalable crossbar matrix (SCM) switch architecture, which consists of multiple crossbar switch units(XSU) with virtual output queues(VOQs) at the inputs and single-cell scheduling decomposition buffers(SDB...

Recently, an innovate switch architecture named Contention-Tolerant Crossbar switch, CTC(N), was proposed. Without resolving output contentions, the controllers are able to fully distributed in CTC(N). It largely reduces the scheduling complexity. However, It has been proved that the saturated switch throughput is bounded by 63% without any scheduling algorithms. In this paper, we present an i...

Abstract— Conventional input switches usually employ a single crossbar switch fabric to transfer cells from input buffers to output ports. This type of switches suffer from input and output cell contention problems which cause lower performance than for output buffer switches. However, dividing one crossbar fabric into several smaller crossbar fabrics, we can decrease the input and output conte...

Building large crossbar switches for low-latency, highbandwidth interprocessor interconnects in multiprocessor systems is a difficult task because of the many practical limitations of digital electronics. This paper presents a first order design for a crossbar switch which utilizes wavelength tunable vertical-cavity surface-emitting laser (VCSEL) technology and free space optics. Free space opt...

Faculty of Electrical Engineering, Mathematics and Computer Science CE-MS-2011-06 Intensive studies have been conducted to identify the most suitable architecture for high-performance packet switches. These architectures can be classified by queuing schemes, scheduling algorithms and switching fabric structures. The crossbar based switching fabric has been widely agreed to be the most suitable ...