due to the expected increase of defects in circuits based on deep submicron technologies, reliability has become an important design criterion. although different approaches have been developed to estimate reliability in digital circuits and some measuring concepts have been separately presented to reveal the quality of analog circuit reliability in the literature, there is a gap to estimate re...

Current-based tests are the most effective methods available to detect resistive shorts. Delta IDDQ testing is the most sensitive variant and can handle off-state currents of 10-100 mA of a single core. Nevertheless this is not sufficient to handle the next generations of very deep sub-micron technologies. Moreover delay-fault testing and very-low voltage testing are not a real alternative for ...

Burn-in faces significant challenges in recent CMOS technologies. The self-generated heat of each IC in a burn-in environment contributes to larger currents that can lead to further increase in junction temperatures, possible thermal run away, and yield-loss of good parts. Calculations show that the junction temperature is increasing by 1.45X/generation. This paper estimates the increase in jun...

Interconnect will be a major bottleneck for deep sub-micron technologies in the years to come. This dissertation addresses the communication aspect from a power consumption and transmission speed perspective. A model for the energy consumption associated with data transmission through deep sub-micron technology buses is derived. The capacitive and inductive coupling between the bus lines as wel...

The growing demand for high density VLSI circuits the leakage current on the oxide thickness is becoming a major challenge in deep-sub-micron CMOS technology. In deep submicron technologies, leakage power becomes a key for a low power design due to its ever increasing proportion in chip‟s total power consumption. Motivated by emerging battery-operated application on one hand and shrinking techn...

Due to the expected increase of defects in circuits based on deep submicron technologies, reliability has become an important design criterion. Although different approaches have been developed to estimate reliability in digital circuits and some measuring concepts have been separately presented to reveal the quality of analog circuit reliability in the literature, there is a gap to estimate re...

As transistor geometries are reduced, leakage current increases. Due to increased levels and process variation, IDDQ test faces difficult challenges for deep sub-micron technologies. Several solutions have been proposed in the literature. This paper provides an overview of some of the solutions. Some views on the future of IDDQ testing are also presented.

Interconnect will be a major bottleneck for deep sub-micron technologies in the years to come. This dissertation addresses the communication aspect from a power consumption and transmission speed perspective. A model for the energy consumption associated with data transmission through deep sub-micron technology buses is derived. The capacitive and inductive coupling between the bus lines as wel...