A novel four-quadrant analog multiplier using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. The drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement the quarter square identity by utilizing only six FGMOS transistors. The main features of this rem...

,4Mrad —A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law characteristics of the MOS transistor. Two versions have been realized. The first has a linearity better than 0.14 percent for an orrtpnt current swing of 36 percent of the supply current and a bandwidth from dc to 1 MHz. The second version has floating inputs, a li...

AbIn this paper a CMOS feurqnadrant d o g enrrent mpltiplkr b dcrerikd. 'Ik drcllit b b.sed om tbe scpu+-lnw eLrvtaWicduMOSb.nsisbrandb~vcbtrmplrture andprocm n r t t i o o r . ~ t h e d n ! n i t i s b t i v e t o t h e body effect eo It b wt mecesmqb place tnnsbtwa i. individd web. TLC mdtijdk has a -3dB budrridtb (Se MAZ uitb lOum k s b t e m ) and an approximately camstant hput impedance Tb...

A study and comparison between current mode CMOS analog multiplier, CMOS current mode multiplier/divider and high frequency four quadrant current multiplier has been carried out in this paper. Current multiplier has been simulated in SPICE with 0.35μm, 0.5μm. Simulation have been done with supply voltage of 3.3V, 1.5V and 1.55V respectively. The simulated results show that characteristic of mul...

Versatile dual-mode class-AB CMOS four-quadrant analog multiplier circuit is presented. The dual translinear loops and current mirrors are the basic building blocks in realization scheme. This technique provides; wide dynamic range, wide-bandwidth response and low power consumption. The major advantages of this approach are; its has single ended inputs; since its input is dual translinear loop ...

In this paper a voltage mode four quadrant analog multiplier (FQAM) using voltage differencing buffered amplifier (VDBA) based on quarter square algebraic identity is presented. In the proposed FQAM the passive resistor can be implemented using MOSFETs operating in saturationregion thereby making it suitable for integration. The effect of non idealities of VDBA has also been analyzed in this pa...

Multiplier is an important block of wireless communication system. In many applications there is a need to mix the signals of different frequencies or signals of different types, which emphasises the use of mixers or multipliers for different RF applications. MOS analog multiplier with less number of transistors which can operate at ISM Band frequency with high linearity is proposed. An ISM ban...

This paper presents, a new current mode four-quadrant CMOS analog multiplier/divider based on dual translinear loops. Compared with the previous works this circuit has a simpler structure resulting in lower power consumption and higher frequency response. Simulation results, performed using HSPICE with 0.25um technology, confirm performance of the proposed circuit.

Equation 1 is the general idealized exponential expression for the emitter current Ie of a BJT in forward active operation. The logarithmic relationship is applicable over several orders of magnitude of collector current. Apply this expression to each transistor in the differential configuration (assume ß >> 1 so that emitter current ≈ collector current); the difference of the expressions for t...