Continual scaling of the CMOS technology requires thinner gate dielectric to maintain high performance. However, when moving into the sub-45 nm CMOS generation, the traditional poly-Si gate approach cannot effectively reduce the gate thickness further due to the poly-depletion effect. Fully silicided Ni metal gate (FUSI) has been proven to be a promising solution. Ni FUSI metal gate can signifi...

The polycrystalline nature of the metal gate and the corresponding non-uniformity in the gate workfunction results in statistical variability in MOSFETs with high-!/metal gate stacks. Here the impact of the workfunction variation (WFV) associated with different gate grain orientations on the threshold voltage variation in a test bed 35 nm nMOSFETs is studied in details using full scale 3D numer...

Conventionally polysilicon is used in MOSFETs for gate material. Doping of polysilicon and thus changing the workfunction is carried out to change the threshold voltage. Additionally polysilicon is not favourable as gate material for smaller dimensional devices because of its high thermal budget process and degradation due to the depletion of the doped polysilicon, thus metal gate is preferred ...

Leakage current reduction is of primary importance as the technology scaling trends continue towards deep sub-micrometer regime. One of the leakage mechanisms which contribute significantly to power dissipation is the Gate Induced Drain Leakage (GIDL). GIDL sets an upper limit on the VLSI MOSFET scaling and may even lead to device breakdown. Thus, in order to improve performance, static power c...

The paper reviews our recent progress and current challenges in implementing advanced gate stacks composed of high-j dielectric materials and metal gates in mainstream Si CMOS technology. In particular, we address stacks of doped polySi gate electrodes on ultrathin layers of high-j dielectrics, dual-workfunction metal-gate technology, and fully silicided gates. Materials and device characteriza...

Junctionless Nanowire Field-Effect Transistors (JNFETs), where the channel region is uniformly doped without the need for source-channel and drain-channel junctions or lateral doping abruptness, are considered an attractive alternative to conventional CMOS FETs. Previous theoretical and experimental works [1][2] on JNFETs have considered polysilicon gates and silicon-dioxide dielectric. However...

Continual evolution of the CMOS technology requires thinner gate dielectric to maintain high performance. However, when moving into the sub-65 nm CMOS generation, the traditional poly-Si gate approach cannot effectively reduce the gate thickness further due to the poly-depletion effect. Fully silicided metal gate (FUSI) has been proven to be a promising solution. FUSI metal gate can significant...

In this paper, we propose a new heterostructure dual material gate junctionless field-effect transistor (H-DMG-JLFET), with negative differential resistance (NDR) characteristic. The drain and channel material are silicon and source material is germanium. The gate electrode near the source is larger. A dual gate material technique is used to achieve upward band bending in order to access n-i-p-...

In dual workfunction gate technologies it can be observed, that p+ poly gates of pMOSFETs tend to lose boron doping. This work presents a model for the transport of Si and B in the TiSi~/polysilicon bilayer system that can explain the saturation of the B dose loss.