This paper presents a design CAD tool for automated of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, multi-objective optimization approach based on genetic algorithms (GA) is proposed and transistor sizes are calculated analytical equations describing behavior circuit. The algorithm developed in MATLAB designed verified using HSPICE simulations...

AbstmctTwo new DAC modeling techniques based on principles of wavelet theory are described in this paper. Macro model and mathematical model are developed for analog and digital circuit simulation, respectively for fast and accurate results using exponential function, damped sine wave, and linear waveform. An 8 bit DAC has been implemented to simulate and evaluate the models. The INLs of the ma...

This paper presents a novel, simple and accurate delay estimation model for single interconnect and tree interconnects, which is based on new matrix Pade-type approximant (MPTA). The proposed model provides a simpler rational function approximation for estimating delay and overshoot in lossy VLSI interconnects. Computational complexity is reduced by considering rational function denominator as ...

A compact but accurate HSPICE macromodel for singlebit resistive RAM (ReRAM) is proposed in this paper. This compact macromodel uses the minimum number of circuit elements to improve the HSPICE simulation speed. And, the macromodel is verified to show very good agreement with the measurements due to voltagecontrolled resistors used as the SET and RESET resistors in the macromodel describing wel...

in this article different types of artificial neural networks (ann) were used for cntfet (carbon nanotube transistors) simulation. cntfet is one of the most likely alternatives to silicon transistors due to its excellent electronic properties. in determining the accurate output drain current of cntfet, time lapsed and accuracy of different simulation methods were compared. the training data for...

This paper presents a two stage operational transconductance amplifier realized using floating gate MOSFETs in differential inputs. A configuration of two stage operational transconductance amplifier using floating gate MOSFET for low power and low voltage applications is presented. Here we design a two stage operational transconductance amplifier using floating gate MOSFET in HSPICE 180nm CMOS...

This paper presents a novel matrix unit cell scheduler (MUCS) for input-bu ered ATM switches. The MUCS concept originates from a heuristic strategy that leads to an optimal solution for cell scheduling. Numerical analysis indicates that input-bu ered ATM switches scheduled by MUCS can utilize nearly 100% of the available link bandwidth. A transistor-level MUCS circuit has been designed and veri...

A neuro-fuzzy network approach is developed to model the nonlinear behavior of submicron metal-oxide semiconductor field-effect transistors (MOSFETs). The proposed model is trained and implemented as a MOSFET in a software environment. The training data are obtained through various simulations of a MOSFET Berkeley short channel insulated-gate field-effect transistor model 3 (BSIM3) in HSPICE, a...

The comparator is designed in pipelined ADC. FINFET is the technology which performs the dual gate MOSFET. This thesis focuses on the high-speed design of pipelined ADC. In the meanwhile, we try to minimize the power dissipation as well. In this thesis, A semidigital Gm-based amplifier is proposed for a low-power pipelined analog-to-digital converter (ADC )in HSPICE .And also we compare the pow...