«Majority Logic Synthesis»
۹۴۳ نتیجهNew Data Structures and Algorithms for Logic Synthesis and Verification
The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics. The continuous downscaling of CMOS Field Effect Transistor (FET) dimen
A portable parallel algorithm for logic synthesis using transduction
Combinational logic synthesis is a very important phase of VLSI system design. But the logic synthesis process requires large computing times if near optimal quality of the logic network is desired. Parallel processing is fast becoming an attractive solution to reduce the computa
Ancilla-free Reversible Logic Synthesis via Sorting
Reversible logic synthesis is emerging as a major research component for post-CMOS computing devices, in particular Quantum computing. In this work, we link the reversible logic synthesis problem to sorting algorithms. Based on our analysis, an alternative derivation of the worst
Two-Level Logic Synthesis for Probabilistic Computation∗
A classical problem in logic synthesis is to find a sum-of-product (SOP) Boolean expression with the minimum number of product terms that implements a Boolean function. In this paper, we focus on a related yet different synthesis problem targeted toward probabilistic computation.
BDD Decomposition for Efficient Logic Synthesis
There are two major approaches to the synthesis of logic circuits. One is based on a predominantly algebraic factorization leading to AND/OR logic optimization. The other is based on classical Reed-Muller decompositionmethod and its related decision diagrams, which have been show
Logic synthesis for PAL-based CPLD-s based on two-stage decomposition
A PAL-based (PAL – Programmable Array Logic) logic block is the core of a great majority of contemporary CPLD (Complex Programmable Logic Device) circuits. The purpose of the paper is to present a novel method of two-stage decomposition dedicated for PAL-based CPLD-s. The key poi
ESOP Transformation to Majority Gates for Quantum-dot Cellular Automata Logic Synthesis
We investigate the benefit of using ESOP minimization in the synthesis of quantum-dot cellular automata (QCA). We determine the size and delay of multi-input XOR and AND/OR gates when implemented in using 3-input majority gates that are easily realized in QCA, and use our results
ARASP: An ASIP Processor for Automated Reversible Logic Synthesis
Reversible logic has been emerged as a promising computing paradigm to design low power circuits in recent years. The synthesis of reversible circuits is very different from that of non-reversible circuits. Many researchers are studying methods for synthesizing reversible combina
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraints solving, determinization, state machine minimization, structural mapping, functional decomposition
Detection of Stuck at Fault Indigital Circuits at Register Transfer Logic (RTL)
Due to the increasing complexity of modern circuit design, verification has become the major bottleneck of the entire design process. Most efforts are to verify the correctness of the initial Register-Transfer Level (RTL) descriptions written in Hardware Description Language (HDL