The primary goal of the register allocation phase in a compiler is to minimize register spills to memory. Spill decisions by the allocator are often made based on the costs of spilling a virtual register and, therefore, on an assumed placement of spill instructions. However, because most allocators make these decisions incrementally, placement opportunities can change as allocation proceeds, ca...

In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate register placement to locations that enable further less clock routing wirelength. To minimize adverse i...

With VLSI design development, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength an...

Nowadays, bulk of the designers prefer to outsource some parts of their design and fabrication process to the third-part companies due to the reliability problems, manufacturing cost and time-to-market limitations. In this situation, there are a lot of opportunities for malicious alterations by the off-shore companies. In this paper, we proposed a new placement algorithm that hinders the hardwa...

ly, data placement definitions are functions that map values onto machine resources. The functions take a value and corresponding attributes (such as data type) and decide where the value belongs. More precisely, placement definitions are finite state machines, since the mapping is order-dependent. Figure 2 illustrates an application of a placement definition to place procedure arguments. In th...

In this paper, we introduce a new placement problem movitated by the Dynamically Reconfigurable FPGA (DRFPGA) architectures. Unlike traditional placement, the problem for DRFPGAs must consider the precedence constraints among logic components. For the placement, we develop an effective metric that can consider wirelength, register requirement, and power consumption simultaneously. With the cons...

This work presents methods for interconnect optimization while performing register optimization and placement of registers in memory. It has been shown that the port assignment problem is similar to the register optimization problem that also considers interconnect optimization. The basic formulation of the register-interconnect optimization problem has been posed as that of finding a clique co...

This paper proposes a common global variable reassignment and an integrated approach which takes advantage of the complementary relationship of inlining and interprocedural register allocation to reduce the procedure call overhead without causing additional negative effect. Our approach is based on the observation of analyzed program characteristic t o identify the heavy called procedures regio...

The development of display scan drivers is an essential step in the effort to develop transparent and flexible display devices based on nanowire transistors. Here we report a transparent nanowire-based shift register that functions as the standard logic circuit of a display scan driver. To form the shift register circuits using only n-type nanowire transistors, a novel circuit structure was int...

The placement of an epidural needle is among the most difficult regional anesthetic techniques. Ultrasound has been proposed to improve success of placement. However, it has not become the standard-of-care because of limitations in the depictions and interpretation of the key anatomical features. We propose to augment the ultrasound images with a registered statistical shape model of the spine ...