This work studies the effects of dynamic threshold design techniques on the speed and power of digital circuits. A new dynamic threshold transistor structure has been proposed to improve performances of digital circuits. The proposed switched-capacitor dynamic threshold PMOS (SC-DTPMOS) scheme employs a capacitor along with an NMOS switch in order to effectively reduce the threshold voltage of ...

Ultralow threshold nanolasers have been sought after as power efficient light sources in photonic integrated circuits. Here a single-cell nanobeam laser with a nanoisland quantum well is proposed and demonstrated. Continuous operation at 1.5 μm is achieved at room temperature with an ultralow lasing threshold of 210 nW in absorbed power. The size of the active medium is reduced to 0.7 × 0.25 × ...

Previous efforts to reduce SRAM power have included voltage scaling to the edge of sub-threshold [2] or into the sub-threshold region [3], but only for idle cells. Although some published SRAMs operate at the edge of sub-threshold, none function at sub-threshold supply voltages compatible with logic operating at the minimum energy point. The 0.18μm memory in [4] provides one exception. Consisti...

Sub-threshold operation offers a compelling solution for ultra-low energy applications such as micro-sensors and embedded medical applications, where low energy needs are the primary concern instead of speed. By lowering the supply voltage below the transistors’ threshold voltage, we see a dramatic drop in energy consumption when compared to normal operations, but circuit instability and delay ...

Sub-threshold operation is a compelling approach for energy-constrained applications where speed is of secondary concern, but increased sensitivity to process variation must be mitigated in this regime. With scaling of process technologies, random within-die variation has recently introduced another degree of complexity in circuit design. This thesis proposes approaches to mitigate process vari...

The effect of interface states on the current–voltage characteristics in the sub-threshold region of three different types of III–V based transistor architectures has been studied using a drift–diffusion based numerical simulator. Experimentally extracted interface state density profile is included in the simulation to analyze their effect on the sub-threshold response of InGaAs based MOSFETs, ...

With CMOS technology being scaled to ever smaller dimensions to achieve higher performance and integration levels, power dissipation has become a major concern in modern VLSI designs. Sub-threshold circuits have gained a lot of importance due to ultra low-power consumption. The paper reviews the sub-threshold circuit design. Various body-biasing schemes and logic families for performance enhanc...