New dynamic CMOS ternary logic circuits, which can be used to form a pipelined system with the nonoverlapped two-phase clocks, are p r o p e d and investigated. AU the proposed new dynamic ternary gates do not have dc power dissipations and have full voltage swings. For complex ternary logic, a new circuit structure called the simple ternary differential logic (STDL) is also proposed and analyz...

The aim of this paper is to design Carbon Nanotube Field Effect Transistor-based (CNTFET-based) combinational circuits with improved Power Delay Product (PDP). Ternary logic circuits have attracted substantial interest due to their capability of increasing information content per unit area. As a result, the geometry-dependent threshold voltage of CNTFETs is effectively used to design a ternary ...

due to the high density and the low consumption power in the digital integrated circuits, mostly technology of cmos is used. during the past times, the metal oxide silicon field effect transistors (mosfet) had been used for the design and implementation of the digital integrated circuits because they are compact and also they have the less consumption power and delay to the other transistors. b...

Today, multipliers are included as substantial keys of many systems with high efficiency such as FIR filters, microprocessors and processors of digital signals. The efficiency of the systems are mainly evaluated by their multipliers capability since multipliers are generally the slowest components of a system while occupying the most space. Multiple Valued Logic reduces the number of the requir...

We present a subquadratic ternary field multiplier based on the combination of several variants of the Karatsuba-Ofman scheme recently published. Since one of the most relevant applications for this kind of multipliers is pairing computation, where several field multiplications need to be computed at once, we decided to design a k-stage pipeline structure for k = 1, . . . , 4, where each stage ...

Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce low-power nano-scale embedded and Internet Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based half adder (THA) multiplier (TMUL) use novel unary operator implement two power ...

An In-depth analysis of the INT05 tritium-production—blanket design Is presented. A ternary system of solid silicate breeder, lead neutron multiplier, and graphite moderator is explored primarily from safety and blanket tritium-inventory considerations. Lithiumsilicate (Li2Si03) bleeder systems are studied along 2 with water (H2P/D2O) and Type 316 stainless steel as coolant and structural mater...

This paper presents a ternary half adder and 1-trit multiplier using carbon nanotube transistors. The proposed circuits are designed pass transistor logic dynamic logic. Ternary uses less connections than binary logic, voltage changes required for the same amount of data transmission. Carbon transistors have advantages over MOSFETs, such as mobility electrons holes, ability to adjust threshold ...

An MOS ternary-logic family is proposed, which is comprised of a set of inverters, NOR gates, and NAND gates. These gates are used to design basic ternary arithmetic and memory circuits. The circuits thus obtained are then used to synthesize complex ternary arithmetic circuits and shift registers. The ternary circuits developed are shown to have some significant advantages relative to other kno...