The design and architecture of a reconngurable memory BIST unit is presented. The proposed memory BIST unit could accommodate changes in the test algorithm with no impact to the hardware. Diierent types of march test algorithms could be realized using the proposed memory BIST unit and the proposed architecture allows addition and elimination of the memory BIST components. Therefore memories wit...

In today’s Integrated Circuits (ICs), Built-In-Self Test (BIST) is becoming increasingly important as designs become more complicated. BIST is a design technique that allows a circuit to test itself Test pattern generator (TPG) using Linear Feedback Shift Resister (LFSR) is proposed which is more suitable for BIST architecture.In this paper we have design ALU (arithmetic and logic unit) in VHDL...

3⁄4 In order to accomplish a high speed test on low speed Automatic Test Equipment (ATE), a new instruction based, fully programmable memory, Built-in Self-Test (BIST) is proposed. The proposed memory BIST generates a high speed internal clock signal by multiplying the external low speed clock signal from the ATE. For maximum programmability and small area overhead, the proposed BIST receives t...

This paper presents BIST TPG (built in self test) for low power dissipation and high fault coverage a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG subside transitions...

A Built-In Self-Test (BIST) approach that is designed to test the analog portion of mixed-signal systems is described. The majority of the BIST circuitry is located in the digital domain to minimize performance impact on the analog circuitry as well as to facilitate easy and automated synthesis of the BIST circuitry. The BIST approach has been implemented in parameterized VHDL for inclusion in ...

This paper proposes a new BIST (Built-In Self-Test) method for static testing of an ADC (Analog-to-Digital Converter) with transition detection method. The proposed BIST uses a triangle-wave as an input test stimulus and calculates the ADC’s static parameters. Simulation results show that the proposed BIST can test both rising and falling transitions with minimal hardware overhead. key words: A...

Abstract A new approach to optimize a configurable twodimensional (2-D) linear feedback shift registers (LFSR) for both embedded and random test pattern generation in built-in self-test (BIST) is proposed. This configurable 2-D LFSR based test pattern generator generates: 1) a deterministic sequence of test patterns for random-pattern-resistant faults, and then 2) random patterns for random-pat...

This paper presents the integration of a proprietary hierarchical and distributed test access mechanism called HDBIST and a BIST insertion commercial tool. The paper briefly describes the architecture and the features of both the environments and it presents some experimental results obtained on an industrial SoC. 1. The HDBIST architecture HDBIST (Hierarchical-Distributed-Data BIST) is a propr...

FPGAs are attractive devices due to their low development cost and short time-to-market, and widely used not only for reconfigurable purpose but also as applicationdependent embedded devices for low-volume products. This paper presents a scan-based BIST architecture for testing of application-dependent circuits configured on FPGA. In order to build up BIST components such as LFSR, MISR and scan...

The paper is aimed at a new system for generation of suitable BIST (Built-in Self-Test) blocks for effective testing of multiple memories integrated in a SoC (System on Chip). Incoming technologies, chip complexity and increasing clock frequencies give new challenges for testing huge number of embedded SoC memories. SoCs have to be tested after their manufacturing and always during their life-t...