نتایج جستجو برای: Vmin diagram

تعداد نتایج: 62677  

2003
Ivar J. Halvorsen Sigurd Skogestad

The Vmin diagram is introduced to effectively visualize how the minimum energy consumption is related to the feed-component distribution for all possible operating points in a two-product distillation column with a multicomponent feed. The classical Underwood equations are used to derive analytical expressions for the ideal case with constant relative volatility and constant molar flows. Howeve...

2013
Tony Tae-Hyoung Kim

Negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) are critical circuit reliability issues in highly scaled CMOS technologies. In this paper, we analyze the impacts of NBTI and PBTI on SRAM VMIN, and present a design solution for mitigating the impact of NBTI and PBTI on SRAM VMIN. Two different types of SRAM VMIN (SNM-limited VMIN and time-limited VMI...

2003
Ivar J. Halvorsen Sigurd Skogestad

We consider separation of ideal multicomponent mixtures with constant relative volatilities and constant molar flows and at constant pressure. The exact analytical solution of minimum energy in a generalized Petlyuk arrangement for separation of N-component feed into M products has been derived. Interestingly, the minimum-energy solution in a complex integrated Petlyuk arrangement is equal to t...

2015
Arijit Banerjee

As we shrink down devices with technology scaling, process variation increases and it hinders SRAM VMIN scaling. Using peripheral assists, we can further lower the VMIN at the cost of energy and area. However, the SRAM VMIN varies with voltage, temperature and operating frequency variations, and it is hard to determine in real time. Prior work shows theoretically that canary SRAMs using reverse...

2004
Hilde K. Engelien Sigurd Skogestad

The minimum energy requirements of six different heat-integrated multi-effect and three non-integrated distillation arrangements for separating a ternary mixture have been considered. The focus of the paper is on a heat-integrated complex distillation configuration; called a multi-effect prefractionator arrangement. The comparison of the different arrangements is based on the minimum vapour flo...

2005
Hilde K. Engelien Sigurd Skogestad

The minimum energy requirements of six different heat-integrated multieffect and three nonintegrated distillation arrangements for separating a ternary mixture have been considered. The focus is on a heat-integrated complex distillation configuration, called a multieffect prefractionator arrangement. The comparison of the different arrangements is based on the minimum vapor flow rates at infini...

2017
Arijit Banerjee Ningxi Liu Harsh N. Patel Benton H. Calhoun John W. Poulton C. Thomas Gray

A closed loop self-tuning 256kb 6T SRAM with 0.38V-1.2V extended operating range using combined read and write assists and canary-based VMIN tracking is presented. 337X and 4.3X power reductions are achieved using multiple assists and VMIN tracking, respectively; combining both saves 1444X in active power and 12.4X in leakage at the 0.38V. Keywords—self-tuning SRAM; combined assists; canary SRA...

2003
Ivar J. Halvorsen Sigurd Skogestad

We show that the minimum energy requirement for separation of a multicomponent mixture in a three-product Petlyuk arrangement is equal to the minimum energy for the most difficult of the two separations (top/middle or middle/bottom product) in a conventional single column. In the Vmin diagram (part 1 of this series), this is simply the highest peak. These results are based on an analytical solu...

2006
Ivar J. Halvorsen

For a four-component feed, Kaibel (1987) proposed a single dividing wall column (DWC) with two side-streams. We will show that an analytic minimal energy expression for the Kaibel-arrangement is straightforward to deduce based on the methods presented by Halvorsen (2001). The expression is very similar to the expression for the 3-product Petlyuk column. Minimum energy for the generalized nprodu...

2016
Brian Zimmer Pi-Feng Chiu Borivoje Nikolic Krste Asanovic

The presented processor lowers SRAM-based cache Vmin by using three architectural techniques–bit bypass (BB), dynamic column redundancy (DCR), and line disable (LD)–that use low-overhead reprogrammable redundancy (RR) to avoid failing bitcells and therefore increase the maximum bitcell failure rate in processor caches. In the 28nm chip, the Vmin of the 1MB L2 cache is reduced by 25%, resulting ...

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