نتایج جستجو برای: batch sizing

تعداد نتایج: 38213  

Journal: :Annals of the Academy of Medicine, Singapore 2010
Swee Chye Quek Wen X Wu Kit Y Chan Ting F Ho William C Yip

INTRODUCTION The device closure of atrial septal defects has evolved over the years. In the early days of transcatheter occlusion, balloon sizing was used to choose an appropriate sized device. We postulate that balloon sizing does not value-add to the procedure and is unnecessary. MATERIALS AND METHODS Patients who had balloon sizing, with (Group 1, n = 38) or without (Group 2, n = 21) atria...

2016
Daria Battini Christoph H. Glock Eric H. Grosse Alessandro Persona Fabio Sgarbossa

One aspect that has mostly been overlooked in traditional economic lot-sizing is the implication of decisions on manual tasks and workload. Although lot-sizing decisions can have a significant impact on required manual material handling and on human performance, works that consider ergonomic aspects in lot-sizing are rare. This paper presents a model that integrates ergonomic aspect in terms of...

2014
W. Sun

A bushing bearing was required between the aluminum connecting rod and the wrist pin to reduce wrist pin bearing wear in a severe application. The bushing could not be machined after assembly and precise control of bearing clearance was achieved by re-sizing (using a mandrel) after assembly. Re-sizing was a critical operation. Too much re-sizing would loosen the bushing pressfit while too littl...

2005
Nadathur Satish Kaushik Ravindran Matthew Moskewicz David Chinnery Kurt Keutzer

We evaluate the effectiveness of statistical gate sizing to minimize circuit power. We develop reliable posynomial models for delay and power that are accurate to within 5-10% of 130nm library data. We formulate statistical sizing as a geometric program, accounting for randomness in gate delays. For various ISCAS-85 circuits, statistical sizing at a 99.8% target yield provides 25% power reducti...

2010
Lakulish Antani Christophe Delage Pierre Alliez

We address the problem of generating mesh sizing functions from a set of points with specified sizing values. The sizing functions are shown to be maximal and K-Lipschitz, with arbitrary parameter K provided by the user. These properties allow generating low complexity meshes with adjustable gradation. After constructing an additively weighted Voronoi diagram, our algorithm provides fast and ac...

Journal: :Obesity 2008
Avani C Modi Meg H Zeller

The aims of the present study were to develop and validate a new obesity-specific, parent-proxy measure of health-related quality of life (HRQOL), Sizing Them Up. Participants included 220 obese youth (M(age) = 11.6 years, 68% female, 53% African American, M(BMI) = 36.7) and their primary caregivers (88% mothers). Primary caregivers completed a demographics questionnaire and two HRQOL measures:...

Journal: :Human factors 2015
Hongwei Hsiao Jennifer Whitestone Tsui-Ying Kau Brooke Hildreth

OBJECTIVE We evaluated the current use and fit of structural firefighting gloves and developed an improved sizing scheme that better accommodates the U.S. firefighter population. BACKGROUND Among surveys, 24% to 30% of men and 31% to 62% of women reported experiencing problems with the fit or bulkiness of their structural firefighting gloves. METHOD An age-, race/ethnicity-, and gender-stra...

Journal: :journal of nanostructures 2013
n. mir a. r. nikkaran m. nejati-yazdinejad a. a. mir

the purpose of the current research is investigating the phenylalanine removal by using magnetic nanoparticles (fe3o4) from water samples. the effect of ph, contact time and phenylalanine concentration on phenylalanine adsorption efficiency by magnetite nanoparticles are studied in a batch system. transmission electron microscopy (tem), x-ray diffraction patterns (xrd) and fourier transform inf...

1999
Etienne Jacobs

Gate sizing is used to increase the performance and/or decrease the area and/or power dissipation of CMOS circuits. There has been extensive work on gate sizing introducing several different methods, producing mixed results in solving speed, size of benchmark circuits and accuracy. These papers however rarely make comparisons between solving methods and usually only use small benchmarks. We int...

2012
M. Sinduja G. Sathiyabama

This paper describes a transistor sizing methodology for both analog and digital CMOS circuits. Various techniques are used for power optimization in CMOS VLSI circuits. Transistor sizing is one of the important techniques for the determination of circuit performance. The aim of the power optimization is to minimize the power and power-delay product or the energy consumption of the circuit. Thu...

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