نتایج جستجو برای: bus

تعداد نتایج: 23647  

2016
Ying-Chih Chen Ping-Yen Chen Chih-Yu Wen Josep M. Guerrero

This invention relates to a wireless bus information management system, which includes bus stop and vehicle management subsystems. The management signals are transmittable between bus stops and the vehicle. Based on vehicle management signals, the bus stop management subsystem can obtain information about the bus route identification, the number of unoccupied seats, the intention to stop or not...

2008
Mountassar Maamoun Abdelhamid Meraghni Abdelhalim Benbelkacem

This paper describes an efficient Programmable Logic Device (PLD) implementation of the Second-order Extended Physical Addressing, connecting the microprocessor-based systems and the external peripherals. This addressing technique, based on the use of software/hardware systems and reduced physical addresses, enlarges the interfacing capacity of the microprocessor-based systems. The input of our...

2014
Nayan N. Pandya Hemant I. Joshi Bhavik N. Suthar

This paper describes sensitivity indicator method to identify weakest bus of the system. It also describes method of calculating the amount of reactive power to be injected at the load bus to avert the voltage instability as the load on the load bus increases. In this paper IEEE-57 BUS system has been considered. First, the weakest bus is identified using sensitivity indicator method. Then Load...

Journal: :Microprocessors and Microsystems - Embedded Hardware Design 1998
Sangyeun Cho Jinseok Kong Gyungho Lee

Cache only memory architecture has the potential to decrease global bus traffic in shared-bus multiprocessors, thereby reducing the speed gap between modem microprocessors and global backplane bus systems. However, the (huge) size of attraction memory (AM) in each processor node makes it difficult to properly match the access time of its state and tag storage to the bus cycle. This becomes a se...

1996
Sangyeun Cho Jinseok Kong Gyungho Lee

Cache Only Memory Architecture has potential of decreasing global bus traffic in shared bus multiprocessors, reducing the speed gap between modern microprocessors and global backplane bus systems. However, the (huge) size of Attraction Memory (AM) in each processor node makes it difficult to properly match the access time of its state and tag storage to bus cycle. This becomes a serious burden ...

2010
N. B. Hounsell B. P. Shrestha F. N. McLeod S. Palmer T. Bowen J. R. Head

London's bus network is one of the largest and most comprehensive urban transport systems in the world. The contribution of buses is recognised by implementing a series of initiatives including bus priority at traffic signals. London has a long history of the implementation of bus priority at traffic signals. It has kept pace with the development of new technologies by updating its bus priority...

Journal: :Chinese journal of traumatology = Zhonghua chuang shang za zhi 2007
Shu-ming Pan Stephen Hargarten Shan-kuan Zhu

OBJECTIVE There is no safer way to transport a child than a school bus. Fatal crashes involving occupants are extremely rare events in the US. In recent years, school bus transportation began to develop in China. We want to bring advanced experience on school bus safety in Western countries such as the US to developing countries. METHODS We searched the papers related to school bus safety fro...

2009
Nitin Chawla

Trambadia: In the past few years we have used HLS tools for designing SoCs and different types of IP blocks. These include AMBA [Advanced Microcontroller Bus Architecture] bus IP blocks like AXI [Advanced eXtensible Interface], AHB [Advanced High-performance Bus], APB [Advanced Peripheral Bus], AHB-Multilayer, and AMBA cross-bus bridges for AXI, AHB, and APB. Similarly, HLS tools have also been...

Journal: :CoRR 2012
Susumu Matsumae

This paper studies the difference in computational power between the mesh-connected parallel computers equipped with dynamically reconfigurable bus systems and those with static ones. The mesh with separable buses (MSB) is the meshconnected parallel computer with dynamically reconfigurable row/column buses. The broadcast buses of the MSB can be dynamically sectioned into smaller bus segments by...

Journal: :Digital Technical Journal 1994
Andrew P. Russo

The AlphaServer 2100 I/O subsystem contains a dual-level I/O structure that includes the high-powered PCI local bus and the widely used EISA bus. The PCI bus is connected to the server's multiprocessing system bus through the custom-designed bridge chip. The EISA bus supports eight general-purpose EISA/ISA connectors, providing connections to plug-in, industry-standard options. Data rate isolat...

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