This work reports on a heterogeneous integration of resistive memories into the Back-End-of-the-Line of 180 nm standard CMOS foundry chips. A TaOx-based ReRAM technology with materials and processes fully CMOS compatible has been developed and characterized. A low-cost integration method is applied to the developed TaOx-based memories to achieve chip level ReRAM–CMOS integration. The integrated...

Bandgap Reference voltage chip is implemented in 0.25μm CMOS technology with ESD protection. This chip can be designed by using a layout tool micro wind 3.1.7 version. The chip circuit generates a reference voltage of 1.23 V. It can operate between 20oC & 70oC temperature. Band gap core produces a voltage that is insensitive to variation in temperature. It has a unique protection with respect t...

We present a 12.5-Gb/s monolithically integrated optical receiver with CMOS avalanche photodetector (CMOS-APD) realized in 65-nm CMOS technology. The optical detection bandwidth limitation of CMOS-APD due to the carrier transit time is compensated by underdamped TIA. With this optical receiver, 12.5-Gb/s 850-nm optical data are successfully detected with bit-error rate less than 10 at the incid...

– This paper is about the design, simulation and study of a CMOS quaternary logic generator having a single stage CMOS body driven design. The interest of design is that the circuit consists of only one CMOS circuit, reducing the chip area and also only two supply rails is required to drive the complete circuitry. The multi-valued logic generator, designed here is also demonstrated with and wit...

This paper reports on the investigation of charge-transfer noise and lag in CMOS image sensors. Noise and lag are analyzed for buried-photodiode CMOS active-pixel-sensor (APS) devices using a simple Monte-Carlo technique. Since the main mechanism of charge-transfer noise involves carrier emission over a barrier, the results are applicable to the soft reset of photodiode-type CMOS APS devices, a...

This paper describes the design of a novel CMOS binary fulladder structure which incorporates four-valued signalling internally. A biased CMOS pseudo-lineaadder provides a quaternary signal representing the number of ones in the three binary inputs. Three area-ratioed CMOS inverters interpret this to provide three binary signals which, combined in conventional static CMOS logic, generate the su...

A monolithically integrated micro-fluidic biosensor system-on-chip (μBio-SSoC) is first realized in standard CMOS processes. This μBio-SSoC is composed of a CMOS-based microfluidic pump, a polysilicon nanowire (SiNW) biosensor, and driving circuits. With 1.5V driving voltage, the microfluidic pump drives sample-liquids to biosensing area with 34 μm/s flowing velocity. After pumping, the detecti...

In this work, I present a CMOS implementation of a neuromorphic system that aims to mimic the behavior of biological neurons and synapses in the human brain. The synapse is modeled with a memristor-resistor voltage divider, while the neuron-emulating circuit (“CMOS Neuron”) comprises transistors and capacitors. The input aggregation and output firing characteristics of a CMOS Neuron are based o...

A versatile fabrication process that allows users to quickly construct micromachined structures using a one metal, one silicon dioxide film stack on a silicon wafer is presented in this technical report. This simplified process, called Mock CMOS, (a) starts from pre-processed wafers and requires only one photolithography step, (b) provides a conductor material for actuating electrostatic and th...

BACKGROUND Colonic ischemia after aortic reconstruction is a devastating complication with high mortality rates. This study evaluates whether Colon Mucosal Oxygen Saturation (CMOS) correlates with colon ischemia during aortic surgery. MATERIALS AND METHODS Aortic reconstruction was performed in 25 patients, using a spectrophotometer probe that was inserted in each patient's rectum before the ...