In this paper, an energy efficient design of asymmetric high performance low swing CMOS driver receiver pair for driving global on-chip interconnects is proposed. The design is implemented on 90nm CMOS technology using HSPICE. The proposed CMOS driver receiver pair reduces the power by 35.45% as compared to the static driver with conventional level converter (CLC). The design is also compared w...

Dynamic CMOS logic circuits are used in high performance VLSI chips in order to achieve very high system performance. These circuits requires less number of transistors as compare to CMOS logic circuits Dynamic logic circuits are much affected by noise as compared to static CMOS circuit. This is due to the fact that dynamic logic circuits have lower value of switching threshold voltage, which i...

Four different pixel architectures to be used in CMOS based indirect time-of-flight (ToF) rangers were designed, fabricated and characterised. The measured results are presented here for their direct comparison. Sharing a very similar, yet case optimised readout circuitry in each case, three fabricated CMOS rangers were based respectively on a pinned photodiode (PPD), a photogate, and a newly d...

This paper examines the suitability of advanced SiGe BiCMOS and sub 65nm CMOS technologies for applications beyond 80GHz. System architectures are discussed along with the detailed comparison of VCOs, LNAs, PAs and static frequency dividers fabricated in CMOS and SiGe BiCMOS, as required for automotive cruise-control radar, high data-rate radio, and active and passive imaging in the 80GHz to 16...

Abstract: In this paper we present a novel static differential ultra low-voltage (ULV) CMOS logic style. Simulated data for the logic style is presented and compared to related ULV logic styles and complementary CMOS gates. The proposed logic style is aimed for high speed serial adders in ultra low-voltage applications. In terms of energy delay product (EDP) the logic style offers a significant...

Aggressive voltage scaling to 0.5V and below is gaining attention due to the interest of using solar cells for portable systems. Static swapped-body biasing [1] and ultra-dynamic voltage scaling (UDVS) [2] are two representative designs in this respect. However, neither of them offers comprehensive treatment of the related design problems. This paper presents a 230-to-500mV 32b RISC core design...

This paper presents an ultrafast CMOS flash A/D converter design and performance. Although the featured A/D converter is designed in CMOS, the performance is compatible to that of GaAs technology currently available. To achieve high-speed in CMOS, the featured A/D converter utilizes the Threshold Inverter Quantization (TIQ) technique. A 6-bit TIQ based flash A/D converter was designed with the ...

The scaling of CMOS transistors has driven the tremendous growth of the semiconductor industry for the last four decades. However, most experts are saying CMOS is reaching its limits. This paper discusses the technologies that may postponing the scaling limit and the technologies that may replace CMOS when the limit is reached.

In the past Smart Power System-on-Chip (SoC) products were almost exclusively designed on Bipolar-CMOS-DMOS (BCD) technologies. These products address applications as diverse as power management for mobile phones, motor drivers, printer head drivers, automotive bus transceivers and dataline drivers for high speed internet or Voice over IP (VoIP). The trend towards SoC design for lowering form f...

We have been developing low power cryogenic readout electronics for space borne large format far-infrared image sensors. As the circuit elements, a fully-depleted-silicon-on-insulator (FD-SOI) CMOS process was adopted because they keep good static performance even at 4.2 K where where various anomalous behaviors are seen for other types of CMOS transistors. We have designed and fabricated sever...