Scaling of gadgets in mass CMOS engineering helps short direct impacts and increment in spillage. Static arbitrary access memory (SRAM) is required to involve 90% of the zone of Soc. Since spillage turns into the essential variable in SRAM cell, it is actualized utilizing FinFet. FinFet gadgets got to be better option for profound submicron advances. In this paper, 6t SRAM cell is actualized ut...

Scaling of device technology, the leakage power has become the main part of power consumption, which seriously reduces the energy recovery efficiency of adiabatic logic.CMOS devices are shrinking to nanometer regime, increasing the consequences in short channel effects and variations in the process parameters which lead to cause the reliability of the circu it as well as performance. To solve t...

In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and Triple Gate (TG) overlap FinFET structure using 2D and 3D computer simulations respectively. To analyze the scaling limits of FinFET structure, simulations are performed using three variables: finthickness, fin-height and gate-length. From 2D simulation of DG FinFET, it is found that the gate-le...

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the ...

Abstract— FinFet is evolved to overcome Moore's law limitations in nanometer regime. Transconductance circuit produces differential output currents, when differential input voltages are applied. A simple FinFet transconductance circuit structure modified from traditional MOSFET is proposed to preserve both area and power. The proposed design contributes a transconductance gain of 5.247 mA/v for...

A double gate FinFET can reduce drain induced barrier lowering and improve threshold (short channel effects). In this paper, a very important geometrical parameter, that is, the fin width of a FinFET has been analyzed. In this article, a double gate n channel FinFET with a gate length of 20nm has been reported. The transfer characteristics of the FinFET at various fin widths have been obtained ...

INTRODUCTION For technology scaling beyond 20 nm, FinFET transistors will replace the conventional planar geometry. The driving force for the introduction of FinFET architecture is the superior immunity to short-channel effects and the reduction of the effects of process variation on device performance exhibited by the FinFET.[1-4] Figure 1 shows a comparison of architectures of the planar FET ...

Two-dimensional (2D) technology computer-aided design (TCAD) is used to analyze and compare the multi-gate digital performance of the screen-grid field effect transistor (SGrFET) with a finFET. The switching speed of the all-n-type inverter is ten times faster for the n-SGrFET than for the n-finFET, while the noise margins are ∼400 mV for a 1 V supply for both devices. The performance of the co...

Transistor size is decreasing day by day, therefore it is difficult to overcome the problem of short channel effects. For preventing short channel effects, source/drain engineering, substrate engineering & gate engineering have been introduced. According to chronological growth of VLSI Design, there is need of non-conventional structure of MOSFET and researchers are getting shifted in search of...