Reconfigurable coprocessors, most commonly implemented with field programmable gate array (FPGA) technology, have been shown effective in accelerating certain classes of applications. Computation-intense kernels can be selected automatically or by hand for acceleration using the coprocessor. For each kernel selected, aconfiguration must be constructed to implement the computation graph of the k...

We present results from the application of a new methodology based on Parallel and Distributed Genetic Programming (PADGP). It allows us to automatically perform the placement and routing of circuits on reconfigurable hardware. For each of the problems we have dealt with, the methodology finds several different solutions. 1 DESIGN BASED ON FPGAS Field Programmable gate arrays (FPGAs) are powerf...

The dynamic and partial reconfiguration of FPGAs enables the dynamic placement in reconfigurable zones of the tasks that describe an application. However, the dynamic management of the tasks impacts the communications since tasks are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performe...

Every commercially available FPGA supplies high routing capabilities. However, placement and routing are processed by a computer before being sent to the chip. This nonadaptive feature does not fit well with bio-inspired applications such as growing systems or neural networks with changing topology. Therefore we propose a new kind of routing, built in hardware and totally distributed. Unlike pr...

Although the huge reconfiguration latency of the available FPGA platforms is a well-known shortcoming of the current FCCMs, little research in instruction scheduling has been undertaken to eliminate or diminish its negative influence on performance. In this paper, we introduce an instruction scheduling algorithm that minimizes the number of executed hardware reconfiguration instructions taking ...

FPGA placement and routing is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle preventing late-bound hardware and design mapping for reconfigurable systems. We introduce a stochastic search scheme which can achieve comparable route quality to traditional, software-based routers while being amenable...

Rapid increase in transistor density and operating frequency has led to the increase in power densities, exhibiting itself as a high temperature profile. The high temperature spots over an FPGA impact the power, performance, and reliability of the chip, hence should be addressed during the design process. The logic block placement is targeted as the natural starting point to address the non-uni...