In this paper, we present a new contribution for the control of Wind-turbine energy systems, a nonlinear robust control of active and reactive power by the use of the Adaptative Backstepping approach based in double-fed asynchronous generator (DFIG-Generator). Initially, a control strategy of the MPPT for extraction of maximum power of the turbine generator is presented. Thereafter, a new contr...

In this work, the benefits of using 3-D integration in the fabrication of Field Programmable Gate Arrays (FPGAs) are analyzed. A CAD tool has been developed to specify 3-dimensional FPGA architectures and map RTL descriptions of circuits to these 3-D FPGAs. The CAD tool was created from the widely used Versatile Place and Route (VPR) CAD tool for 2-D FPGAs. The tool performs timing-driven place...

Accurate simulations of various physical processes on digital computers requires huge computing performance, therefore accelerating these scientific and engineering applications has a great importance. Density of programmable logic devices doubles in every 18 months according to Moore’s Law. On the recent devices around one hundred double precision floating-point adders and multipliers can be i...

PAM-Blox are object-oriented circuit generators on top of the PCI Pamette design environment, PamDC. Highperformance FPGA design for adaptive computing is simplified by using a hierarchy of optimized hardware objects described in C++. PAM-Blox consist of two major layers of abstraction. First, PamBlox are parameterizable simple elements such as counters and adders. Automatic placement of carry ...

Partial Runtime Reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. We make two contributions in this paper. First, we present an efficient algorithm for finding the complete set of Maximal Empty Rectangles on a 2D PRTR FPGA. We also present a HW implementation of the algorithm with negligible runtime overhead. Second, we present an efficient online deadl...

The square cells specified by Ruby language, called Ruby cells, can be relocated by either rotation, horizontal flip, vertical flip or shifting in a regular array structure such as FPGA (Field Programmable Gate Array) fabric. In this paper, our research has shown that those relocating cells can be specified and reasoned formally by algebraic laws of Ruby algebra and Group theory. As a result, a...

Dynamic reconfiguration is a promising approach to enhance the resource efficiency of FPGAs beyond the current possibilities. One of the main prerequisites for its implementation is a communication infrastructure that enables data transfer between the hardware modules that are placed on the FPGA at run-time. In this paper we present a new communication macro for Xilinx FPGAs that considers the ...

A High-Speed Timing-Aware Router for FPGAs Master of Applied Science, 1998 Jordan S. Swartz Department of Electrical and Computer Engineering University of Toronto Digital circuits can be realized almost instantly using Field-Programmable Gate Arrays (FPGAs), but unfortunately the CAD tools used to generate FPGA programming bit-streams often require several hours to compile large circuits. We c...

In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible failures. Therefore, improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate permanen...

In this work, we present a compact “adaptive downsampling” method that mitigates the nonlinearity problems associated with FPGA-based TDCs utilize delay lines. Additionally, generic allows for trade-offs between resolution, linearity, and resource utilization. Since is one of predominant issues regarding lines in TDCs, combined fact are utilized wide range TDC architectures (not limited to dela...