This paper presents an integrated design system called sparcs (Synthesis and Partitioning for Adaptive Recon gurable Computing Systems) for automatically partitioning and synthesizing designs for recongurable boards with multiple eld-programmable devices (fpgas). The sparcs system accepts design speci cations at the behavior level, in the form of task graphs. The system contains a temporal part...

Field Programmable Gate Arrays (FPGAs) play many important roles, ranging from small glue logic replacement to System-on-Chip (SoC) designs. Nevertheless, FPGA vendors cannot accurately specify the power consumption of their products on device data sheets because the power consumption of FPGAs is strongly dependent on the target circuit, including resource utilization, logic partitioning, mappi...

This paper presents an integrated design system called sparcs (Synthesis and Partitioning for Adaptive Reconngurable Computing Systems) for automatically partitioning and synthesizing designs for recon-gurable boards with multiple eld-programmable devices (fpgas). The sparcs system accepts design speciications at the behavior level, in the form of task graphs. The system contains a temporal par...

Multi-FPGA systems (MFS) are used for a great variety of applications, for instance, dynamically re-configurable hardware applications, digital circuit emulation, and numerical computation. There are a great variety of boards for MFS implementation. In this paper a methodology for MFS design is presented. The techniques used are evolutionary programs and they solve all of the design tasks (part...

An investigation of the implementation and optimization of Beneš Permutation Networks on Field Programmable Gate Arrays (FPGAs) is presented. Specialized design automation tools were used to achieve high performance and efficient area utilization. These tools were used to explore alternative placement and routing strategies, and to take advantage of the underlying FPGA resources. A significant ...

This paper introduces VTsim, a device simulator for Xilinx Virtex-II FPGAs. VTsim is currently a globally synchronous event-driven device simulator modeled at the CLB level. Through use of JBits3 and ADB, VTsim provides designers with the ability to simulate all resources within an FPGA via a virtual device. The simulator has been designed for rapid response, low memory usage, and ease of inter...

In this paper we present an universal module generator for hierarchical carry lookahead adders of any word length which is suitable for most SRAM-based FPGA architectures. We introduce a generic model of SRAMbased FPGAs taking different configurations of the logic blocks into account. Considering the logical structure of CLA adders we efficiently perform technology mapping including an adaptive...

Regularity extraction attempts to find common sub-structures (templates) in one or a collection of circuits (graphs). There are many applications for regularity extraction, including, but not limited to, compiler instruction generation and selection for hybrid (re)configurable systems, scheduling during logic synthesis, system-level partitioning and FPGA mapping and placement. We aim to build a...

Protecting cryptographic implementations against side-channel attacks is a must to prevent leakage of processed secrets. As a celllevel countermeasure, so called DPA-resistant logic styles have been proposed to prevent a data-dependent power consumption. As most of the DPA-resistant logic is based on dual-rails, properly implementing them is a challenging task on FPGAs which is due to their fix...

Dynamic Partially Recon ̄guration (DPR) designs provide additional bene ̄ts compared to traditional FPGA application. However, due to the lack of support from automatic design tools in current design °ow, designers have to manually de ̄ne the dimensions and positions of Partially Recon ̄gurable Regions (PR Regions). The following ̄ne-grained placement for system modules is also limited because it ta...