Field-programmable gate arrays (FPGAs) are becoming an increasingly important implementation medium for digital logic. One of the most important keys to using FPGAs effectively is a complete, automated software system for mapping onto the FPGA architecture. Unfortunately, many of the tools necessary require different techniques than traditional circuit implementation options, and these techniqu...

This work explores the effect of adding a simple functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has completed, alternative decompositions of the logic on the critical path are examined for potential delay improvements. The placed circuit is then modified to use the best decompositions found. Any placement illegalities introduced by...

This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has completed, alternative decompositions of the logic on the critical path are examined for potential delay improvements. The placed circuit is then modified to use the best decompositions found. Any placement illegalities introd...

One of the steps involved in the computer-aided design for FPGA (FieldProgrammable Gate Array) circuits is placement. In this step, the logic functions are assigned to specific cells of the circuit. In conventional hierarchical min-cut based placement algorithms, the layout region is bi-partitioned using slicing lines in a top-down manner. In these placement algorithms, the cut-line is always c...

Field-Programmable Gate Arrays (FPGAs) are one of the most popular platforms for implementing digital circuits. Their main advantages include the ability to be (re)programmed in the field, a shorter time-to-market, and lower non-recurring engineering costs. This programmability, however, is afforded through a significant amount of additional circuitry, which makes FPGAs significantly slower and...

Dynamic Circuit Specialization is used to optimize the implementation of a parameterized application on an FPGA. Instead of implementing the parameters as regular inputs, in the DCS approach these inputs are implemented as constants. When the parameter values change, the design is reoptimized for the new constant values by reconfiguring the FPGA. This allows faster and more resource-efficient i...

The simulated annealing algorithm is an extensively utilized heuristic method for heterogeneous FPGA placement. As the application of neural network models on FPGAs proliferates, new challenges emerge traditional in terms timing. These stem from large circuit sizes and high heterogeneity block proportions typical networks. To address these challenges, this study introduces a timing-driven place...

In this work, we present a genetic algorithm framework for the FPGA placement problem. This framework is constructed based on previous proposals in this domain. We implement this framework in an academic FPGA tool, and run a set of experiments that show that the fine grain genetic mutation approach, previously proposed, is not as good as an existing simulated annealing algorithm. This does not ...