We provide in this thesis our contribution in the area of reconfigurable system synthesis. We consider reconfigurable systems constructed from one or more general purpose processors (GPP) and a set of reconfigurable processing units (RPU). Given an application to be implemented on this architecture, a hardware/software partitioning step is used to differentiate between the part of the applicati...

Soft errors are intermittent malfunctions of hardware that are not reproducible. They may affect the data integrity and affect the system operation. These errors are growing reliability threat in VLSI system design. A soft error occurring in a memory cell or register is called a Single Event Upset (SEU). Designs mapped into Field Programmable Gate Arrays (FGPAs) are more vulnerable to soft erro...

Local search methods such as WSAT have proven to be successful for solving SAT problems. In this paper, we propose two real-time host-FPGA (Field Programmable Gate Array) co-implementations, which use modified WSAT algorithms to solve SAT problems. Our implementations are reconfigurable in real-time for different problem instances. On an XCV1000 FPGA chip, SAT problems up to 100 variables and 2...

A CAD tool has been developed to specify 3-dimensional FPGA architectures and map RTL descriptions of circuits to these 3-D FPGAs. The CAD tool was created from the widely used VersatilePlace and Route (VPR) CAD tool for 2-D FPGAs. The tool performs timing-driven placement of logic blocks in the 3-dimensional grid of the FPGA using a two-stage Simulated Annealing (SA) process. The SA algorithm ...

Design automation or computer-aided design (CAD) for field programmable gate arrays (FPGAs) has played a critical role in the rapid advancement and adoption of FPGA technology over the past two decades. The purpose of this paper is to meet the demand for an up-todate comprehensive survey/tutorial for FPGA design automation, with an emphasis on the recent developments within the past 5–10 years....

This paper presents an FPGA design methodology that can be used to shorten the FPGA design-and-debug cycle, especially as the gate counts increase to multi-millions. Core-based incremental placement algorithms, in conjunction with fast interactive routing, are investigated to reduce the design processing time by distinguishing the changes between design iterations and reprocessing only the chan...

Partial runtime reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. We make two contributions in this paper. First, we present an efficient algorithm for finding the complete set of Maximal Empty Rectangles on a 2D PRTR FPGA. We also present a HW implementation of the algorithm with negligible runtime overhead. Second, we present an efficient online deadl...

This report summarizes my Ph.D. research progress from March 2001 to March 2002. This time period corresponds to part of the third and fourth year of my Ph.D. candidacy. As stated in my first report, the goal of my Ph.D. research is to create an efficient FPGA architecture for datapath circuits. My research methodology is empirical and consists of three phases, two of which have been completed ...

This paper describes the stochastic-based Spin-Programmable Gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to replace configuration memory in field programmable gate arrays (...

As FPGA densities increase, partitioning-based FPGA placement approaches are becoming increasingly important as they can be used to provide high-quality and computationally scalable placement solutions. However, modern FPGA architectures incorporate heterogeneous resources, which place additional requirements on the partitioning algorithms because they now need to not only minimize the cut and ...