In this paper, we describe the development of device models and tools for the design of the carbon nanotube FET (CNFET). Both HSPICE model and Verilog-A model for CNFET including typical device/circuit level non-idealities have been developed. They can be used for design of nanotube transistor circuits as well as to study performance benefits of the new transistor.

A current reference with low temperature sensitivity based on a switched-capacitor technique has been developed. The implementation is targeted for a 0.18μ CMOS process. HSPICE simulations using level 49 models valid over a wide temperature range were used to verify the design. The simulation results predict variations of less than 0.029% over a temperature range of –40 °C to 125 °C.

This paper presents, a new current mode four-quadrant CMOS analog multiplier/divider based on dual translinear loops. Compared with the previous works this circuit has a simpler structure resulting in lower power consumption and higher frequency response. Simulation results, performed using HSPICE with 0.25um technology, confirm performance of the proposed circuit.

In this paper a new geometric-mean circuit for current-mode square-root domain filters (SRD) is presented. The geometric-mean circuit employs MOSFET transistors that are operating in both strong inverted saturation and triode regions and works in low supply voltage. Simulation results by HSPICE confirm the validity of the proposed design technique.

A novel mixed mode current and dynamic voltage CMOS 1-bit full adder cell is presented. In this new design, by combination of voltage and current mode circuits and adopting the advantage of each circuit in the finest way, we obtain the highest possible speed. The results are validated through HSPICE Simulation with 0.18 um and 1.8v, Vdd.

Abstract This paper proposes a design of gate all around CNTFET based ternary content addressable memory (TCAM). TCAM cell is designed and simulated in HSPICE using top gated (TG-CNTFET) & CNTTFET (GAA-CNTFET). Dual chirality technique used to i.e. different for n-type p-type which utilizes threshold voltages hence improve the performance. Comparative analysis has been done various paramete...

This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in dynamic comparators. In this scheme, feedback loop is designed using the characteristics of comparator; monitoring voltage can determine presence circuit fault. The proposed BIST and under testing are realized at transistor level. was simulated HSPICE. fault coverage approximately 87.8% with 90 test circ...

Memristor, as an innovative technology, has been proposed in the application of neural networks since its physical implementation was reported by HP lab. In this paper, we proposed a Hamming network circuits based on CMOS/memristor hybrid design which is compact in device size and circuit structure. Through HSPICE simulation, pattern recognition and classification functions of hamming network c...

A Novel circuit configuration for realizing multi-output four-terminal floating nullor in biopolar monolithic integrated circuit form is described. The circuit is simple and based on the use of an improved translinear cell type circuit, which provide wide bandwidth and dynamic range. The characteristics of this circuit are confirmed by HSPICE simulation results. The performance of the FTFN-base...

Parallel analog circuits are introduced for the solution of systems of nonlinear algebraic equations and the integration of systems of differential equations. Both simulations using HSPICE and a hardware implementation are presented which show how the circuitry can be used to solve: the power flow and transient analysis problems for power systems, and the simulation of a jet engine. In all case...